Networks-on-Chip (NoCs) interconnection architectures to be used in future billion-transistor Systems-on-Chip(SoCs) meet the major communication requirements of these systems, offering, at the same time, reusability, scalability and parallelism in communication. Furthermore, they cope with other issues like power constraints and clock distribution. Currently, there is a number of research works which explore different features of NoCs. In this paper, we present SoCIN, a scalable network based on a parametric router architecture to be used in the synthesis of customized low cost NoCs. The architecture of SoCIN and its router are described, and some synthesis results are presented.

The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

This work analyzes the mapping of applications onto generic regular Networksen-Chip (NoCs). Cotes must be placed considering communication requirements, so as to minimize the overall application execution time and energy consumption. We expand previous mapping strategies by taking into consideration the dynamic behavior of the target application and thus potential contentions in the intercommunication of the cores. Experimental results for a suite of 22 benchmarks and various NoC sizes show that a 42% average reduction in the execution time of the mapped application can be obtained, together with a 21% average reduction in the total energy consumption far state-. of-the-art technologies.

Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP cores and advanced interconnection schemes, such as hierarchical bus architectures or networks on chip (NoCs). Modeling applications involves capturing its computation and communication characteristics. Previously proposed communication weighted models (CWM) consider only the application communication aspects. This work proposes a communication dependence and computation model (CDCM) that can simultaneously consider both aspects of an application. It presents a solution to the problem of mapping applications on regular

No abstract

Abstract-The wide use of Multi-processing systems-on-chip (MPSoCs) in embedded systems and the trend to increase the integration between devices have turned these systems vulnerable to attacks. Malicious software executed on compromised IP may become a serious security problem. By snooping the traffic exchanged through the Network-on-chip (NoC), it is possible to infer sensitive information such as secrets keys. NoCs are vulnerable to side channel attacks that exploit traffic interference as timing channels. When multiple IP cores are infected, they can work coordinately to implement a distributed timing attack (DTA). In this work we present for the first time the execution of a DTA and a secure enhanced NoC architecture able to avoid the timing attacks. Results show that our NoC proposal can avoid the DTA with an increase of only 1% in area and 0.8% in power regarding the whole chip design.

No abstract

Present days cores composing a System-on-Chip might be interconnected by means of both dedicated channels or shared buses. Nevertheless, future systems will have strong requirements on reusability and communication performance, which will constrain the use of such interconnect systems. An emerging approach, the Networks-on-Chip (NOCs), will potentially fulfill those requirements, because NOCs are reusable and their communication performance gracefully scales with the system growth. However, it is still not clear when the use of NOCs will become mandatory. This work introduces some studies to define the switching point when NOCs become the preferred communication architecture. A bus and a NOC are modeled and compared by using a set of mathematical models.