Abstract-The wide use of Multi-processing systems-on-chip (MPSoCs) in embedded systems and the trend to increase the integration between devices have turned these systems vulnerable to attacks. Malicious software executed on compromised IP may become a serious security problem. By snooping the traffic exchanged through the Network-on-chip (NoC), it is possible to infer sensitive information such as secrets keys. NoCs are vulnerable to side channel attacks that exploit traffic interference as timing channels. When multiple IP cores are infected, they can work coordinately to implement a distributed timing attack (DTA). In this work we present for the first time the execution of a DTA and a secure enhanced NoC architecture able to avoid the timing attacks. Results show that our NoC proposal can avoid the DTA with an increase of only 1% in area and 0.8% in power regarding the whole chip design.
Many authors have shown how to break the AES cryptographic algorithm with side channel attacks, specially the timing attacks oriented to caches, like Prime+Probe. In this paper, we present a practical timing attack on NoC that improves Prime+Probe technique. Our attack targets the communication between an ARM Cortex-A9 core and a shared cache memory. Furthermore, we evaluate a secure enhanced NoC applied as a countermeasure of the timing attack. Finally, we demonstrate that attacks on MPSoCs through the NoC are a real threat and need to be further explored.
The increasing use of mobile electronic devices forces the design of integrated circuits to consider low power techniques. Current power estimation models for oCs capitalize mostly in the volume of information transmitted through the network. This work presents a more precise oC power estimation model, based in buffer reception rates, according to the traffic scenario applied to the network. Results show the accuracy of the model compared to industrial power estimation tools, with reduced execution time. The proposed method allows exploring the oC design space, being employed to evaluate the benefit on using the multicast service.
Due to the vast number of alternatives in the design space of NoCbased MPSoCs, fast and accurate performance evaluation approaches can result in earlier -and often better -design decisions. Important design metrics for mobile embedded systems include power dissipation and energy consumption. To speed-up the evaluation of such metrics, state-of-the-art research proposes abstract models of the NoC interconnect, employing, for example, TLM SystemC, analytical descriptions and graph descriptions. Power parameters used at higher abstraction models (e.g. TLM) frequently rely upon data generated at lower abstraction levels (e.g. RTL). This paper presents an abstract model of a NoC coupled with a power estimation model, aiming to provide accurate estimations early on the design flow. Despite being abstract, this model considers typical NoC communication behavior such as congestion and burst transmissions, leading to accurate results compared to industrial tools. A proof-of-concept implementation using the Ptolemy II framework demonstrates the strength of this approach, showing that it is possible to use abstract models to estimate power and energy without incurring excessive accuracy loss. Other benefits of abstract modeling are increased system observability and simplicity of design space exploration. System observability is demonstrated with a graphic tool enabling the visualization of the power dissipation at runtime.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citationsâcitations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.