Hardware integrated quantization solution for improvement of computational H.264 encoder module

Abstract

The computational module of several MPEG-based video encoders, which includes the known algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization, is widely used to identify and compress spatial redundancy in intra (raw input) or inter (computed residue) data pixel matrices. For some modern multimedia applications, like high definition (HD H.264/AVC) or scalable (H.264/SVC) encoder solutions, the demand for fast module implementations becomes critical. Practical experiments indicate that, inside a H.264 computational module, the quantization module normally represents a real bottleneck for fast hardware implementations. Considering that we propose a complete integrated solution of H.264 computational module, which incorporates the direct and inverse algorithms of Discrete Cosine Transform, Hadamardand Quantization with minimal communication delays. Also in this paper it is presented a practical study, considering distinct levels of parallelism for the quantization to demonstrate its influence in order to optimize global encoder complexity and performance. All proposed alternatives were designed using hardware description language VHDL and implemented into commercial FPGA boards to obtain experimental results.

A Cost-Shared Quantization Algorithm and Its Implementation for Multi-Standard Video Codecs

“…The 8x8 transform and quantization for H.264 is presented in [20] and [21]. Several other designs based on H.264 codec have been reported in [22][23][24][25][26][27]. The authors in [28] present a design for the quantization for AVS.…”

“…In Table 5 Moreover it also has four parallel adders. As compared to the design presented in [24] the proposed multi quantizer has only one shared multiplier and one shared adder to support all the six standards. As the quantization unit of [24] has several multipliers and several adders it increases the cost of the architecture.…”

“…As compared to the design presented in [24] the proposed multi quantizer has only one shared multiplier and one shared adder to support all the six standards. As the quantization unit of [24] has several multipliers and several adders it increases the cost of the architecture. Here the hardware cost of the multi quantizer is compared with the quantization unit of [24].…”

“…As the quantization unit of [24] has several multipliers and several adders it increases the cost of the architecture. Here the hardware cost of the multi quantizer is compared with the quantization unit of [24]. The authors in [25] present a 4x4 transform and quantization.…”

Variable Bit-Depth Processor for 8×8 Transform and Quantization Coding in H.264/AVC

“…An inverse quantization that adopts three kinds of inverse quantizers based on prediction modes and coefficients used in a H.264/AVC decoder was presented in (Chao et al, 2009). (Husemann et al, 2010) proposed a four forward parallel quantizer architecture implemented in a commercial FPGA board. We propose a single circuit to compute the forward quantization and rescaling for different bit-depth requirements.…”