The computational module of several MPEG-based video encoders, which includes the known algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization, is widely used to identify and compress spatial redundancy in intra (raw input) or inter (computed residue) data pixel matrices. For some modern multimedia applications, like high definition (HD H.264/AVC) or scalable (H.264/SVC) encoder solutions, the demand for fast module implementations becomes critical. Practical experiments indicate that, inside a H.264 computational module, the quantization module normally represents a real bottleneck for fast hardware implementations. Considering that we propose a complete integrated solution of H.264 computational module, which incorporates the direct and inverse algorithms of Discrete Cosine Transform, Hadamardand Quantization with minimal communication delays. Also in this paper it is presented a practical study, considering distinct levels of parallelism for the quantization to demonstrate its influence in order to optimize global encoder complexity and performance. All proposed alternatives were designed using hardware description language VHDL and implemented into commercial FPGA boards to obtain experimental results.

It is challenging to obtain good results for hand movements classification. Previous studies expended efforts on filters for sEMG data, feature extraction and classifier algorithms to achieve the best results. This paper proposes the insertion of a step in the classification process that selects which features to use in training aiming to increase accuracy and performance. Feature selection was previously used in other classification tasks but is new in wrist/fingers movements classification. Obtained results were positives as the performance gain is huge (39 to 53 features out of 144 are used for classification) and accuracy reach promising values (above 90% for some subjects).

The computational-intensive demands of H.264 video encoder normally imply to the use of high performance hardware solutions like dedicated multimedia DSP or programmable logic devices. These demands can be even more critical when it is necessary to implement a H.264/SVC (Scalable Video Coding) solution, an emergent encoder standard that provides the generation of flexible and adaptive multi-layer streams. The complexity of a SVC encoder increases proportionally with number of configured layers, introducing new challenges to multimedia market. In this work we propose an efficient hardware module, responsible for the transform algorithms (Hadamard and DCT) of a SVC encoder, processing up eight samples per clock. The proposed module take into account specific memory demands in order to produce an optimized solution with respect to encoder performance and complexity, aiming to reach a realizable SVC encoder.

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