Via interconnections for wafer level packaging: Impact of via shape on spray coating behavior

Abstract

The Wafer level Packaging for optical image sensor devices developed by Schott Advanced Packaging utilizes a via trough contact through the Silicon by contacting the bond pads of the image sensors from the backside. Direct contact of the bond pads from the back side of the chip offers much shorter transmission paths to the board assemblies, thus providing faster signal speed, efficient thermal conduction and many added advantages [1], [2].After forming the vias by means of plasma etching [3], the electrical connection from the bottom of the via to the backside of the wafer is done by spray coating and lithography to form the redistribution layer, and prepare the wafer for bumping at a later process step.Via shape and spray coating process are the key to achieve a good quality and reliable product. This paper discusses interactions between the via shape (profile angle and profile shape) and its effect on subsequent spray coating processes. The shape of the via, and its homogeneity over the wafer, significantly affect the performance and stability of the next process steps, thus careful balancing of the via forming process and the spray coating is required.Further, the impact of via stability under production conditions on the spray coating performance is presented.

Photoresist coating and patterning for through-silicon via technology

“…So far in all the reported cases, contact printing was used to pattern the features at the bottom of a deep-etched via or trench [1][2][3][4]. For lithography on a planar surface, when a hard contact mode is applied, the gap between the mask and the resist surface is zero (figure 11(a)).…”

“…In this paper, we study two potential photoresist coating methods for this application: spray coating and electrodeposition (ED) of the photoresist. Although some results on resist coating over high topography using a spray [3,4] or an ED resist [5] have been reported, a study on resist patterning and the influence of the lithography on the patterned features is still lacking.…”

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

“…Such problems can be solved by etching tapered vias using laser ablation or DRIE [210], [211], which facilitates both deposition and patterning. Maskless laser ablation is actually a quite convenient way to pattern the SiO 2 /polymer layer deposited on the via base.…”