Lithography for Patterning inside through-Si Vias

Pham, Nga; Tezcan, Deniz Sabuncuoglu; Majeed, Bivragh; Moor, Piet De; Baert, Kris; Swinnen, Bart; Ruythooren, Wouter

doi:10.1109/eptc.2007.4469729

Cited by 4 publications

(3 citation statements)

References 8 publications

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“…Initial investigation have been reported that discussed spray coating parameters such as resist solution, nozzle scanning speed and dispense rate [9] for TSV application. While the influences of the large gap exposure, resist thickness and resist type on the dimension of resist patterns have been reported in [10]. In this paper, we report on the optimized process for spray coating to pattern the resist at the bottom of the via.…”

Section: Parylene Patterningmentioning

confidence: 97%

Parylene N as a dielectric material for through silicon vias

Majeed

Pham

Tezcan

et al. 2008

2008 58th Electronic Components and Technology Conference

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This paper reports on the feasibility of parylene N as a dielectric material for Through Silicon Vias (TSV). TSV are the key enabling technology for 3D wafer laver packaging. Parylene is used as an insulating material in one of the approaches adopted for realizing 3D wafer level packaging at IMEC. This paper discusses main issues regarding the processing of parylene N for the TSV application. First, the thickness uniformity of as-deposited parylene across the wafer and inside the via is investigated. The results show that for 200mm wafers, within-wafer and wafer-to-wafer thickness is sufficiently uniform. The 1-sigma thickness variation of less than 4 percent for both cases is measured. 1 sigma thickness variation of less than 5 percent is observed from batch to batch. Second, the effect of substrate, temporary glue layer and carrier wafer for thinned device wafers on the dry etching of parylene is analyzed. The experiments show that the etching was sufficiently uniform across the wafer; and the uniformity across the surface is recorded to be greater than 95 percent. There is no considerable effect of substrate or bonding layer thickness, however carrier wafer influence the etching rate. IntroductionTSV is the key technology for realizing many different 3D integration approaches. 3D technologies are becoming one of the main drivers for continuous system miniaturization. Some important challenges still need to be met for high process yields and cost effective processes. IMEC is investigating two different approaches: 3D SiC and 3D WLP [1]. 3D SiC approach aim to create very high density vertical interconnects to allow stacking of die. This approach is also referred as via first, as via are formed before the CMOS processing. It involves formation of silicon via, copper filling, standard CMOS processing followed by bonding wafer to a carrier, thinning down to 20 microns and a CMP step to expose the copper plug. These plugs are then used for make interconnection between different dice. IMEC has demonstrated yielding 10K TSV chains with an average via pitch of 10 microns for a via diameter of 5 micorns [2]. The 3D WLP approach at IMEC, involves developing a sloped TSV with a "circuit first" methodology where the vias are fabricated after CMOS processing. Hence it is a generic approach and compatible with standard IC wafers allowing direct stacking of wafers or die. IMEC has demonstrated yielding via chains of different size ranging from 50-150 microns with the via resistance in the range of 20-30 mohms [3]. This paper will discuss process related to 3D WLP TSV.In our 3D WLP TSV process, the device wafer is first bonded face-down onto a carrier using temporary glue layer

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Section: Parylene Patterningmentioning

confidence: 97%

Parylene N as a dielectric material for through silicon vias

Majeed

Pham

Tezcan

et al. 2008

2008 58th Electronic Components and Technology Conference

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“…The size of the bump is primarily uniform, and none of the bumps showed serious defects, as shown in Figure 16b. Bumping without the lithography method has advantages such as omitting the following steps: PR (photoresist) coating, film masking, UV (ultraviolet) exposure, patterning, and PR stripping processes [76,80]. The author also uses the non-PR process in various studies [9,78,79].…”

Section: Solder Bump By Electroplatingmentioning

confidence: 99%

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Cho

Seo

Kim

et al. 2021

Metals

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With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

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“…Negative photoresist is preferred since only exposure on the wafer surface is required, and not in the TSV cavity, which would introduce nonuniform exposure of the photoresist due to resist thickness variation and the large proximity [3]. The electroplating is done in two steps.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Electrical Evaluation of Via Last Polymer Liner TSVs

Tezcan¹,

Majeed²,

Civale³

et al. 2010

Journal of Microelectronics and Electronic Packaging

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Imec is developing two TSV flavors for Si thicknesses of 50 and 100 fim for various wafer level packaging (WLP) applications where thin dice are stacked and electrically connected to each other through post CMOS processed TSVs and microbumps. As a differentiator, these TSV technologies use spinon dielectric polymers as the insulating liner. A three-mask process sequence is implemented for fabrication of both TSV types; however, the TSV shape, the process flow, and the Si thickness are different for each one of them. All processes employed in the fabrication of the TSVs are performed at low temperature (<200 C) for post CMOS compatibility. For both TSV types, electrically yielding TSV connected daisy chains are measured on the fabricated wafers and the reliability of the TSVs while undergoing thermal cycle tests is analyzed.

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Lithography for Patterning inside through-Si Vias

Cited by 4 publications

References 8 publications

Parylene N as a dielectric material for through silicon vias

Parylene N as a dielectric material for through silicon vias

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Fabrication and Electrical Evaluation of Via Last Polymer Liner TSVs

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