A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Abstract

With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

X‐ray microscopy and automatic detection of defects in through silicon vias in three‐dimensional integrated circuits

“…Furthermore, wall delamination defects that origin from the thermal mismatch of Si and Cu will lead to TSV degradation and is an important reliability failure as it reduces the electrical signal transfer in dies. 15,51,52 Therefore, the types of defects studied in this work are wall delamination defects of Cu liner-TSVs in the micrometer to sub-micrometer range. Overall, the XRM workflow is designed to suit that size range and being able to detect large delamination defects in micrometer range via a full device scan recipe and submicron defects with detailed TSV scan recipe.…”

“…XRM is chosen as a non‐destructive technique that enables a fast defect analysis of a large number of TSVs, such as 70 or more, with defect identification down to the sub‐micron scale. Furthermore, wall delamination defects that origin from the thermal mismatch of Si and Cu will lead to TSV degradation and is an important reliability failure as it reduces the electrical signal transfer in dies 15,51,52 . Therefore, the types of defects studied in this work are wall delamination defects of Cu liner‐TSVs in the micrometer to sub‐micrometer range.…”

Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review

“…This enables the transmission of thermal and electrical signals within the chip, significantly enhancing chip integration and performance. TSV encounters challenges such as differences in the coefficient of thermal expansion between filling materials and adjacent materials, resulting in thermal mismatch issues and interface cracking or delamination under thermal stress [4,5]. Furthermore, parasitic effects in TSV structures in high-frequency environments can impact signal transmission efficiency [6].…”

Artificial intelligence deep learning for 3D IC reliability prediction

“…There are several key interconnection technologies, such as Through-Si-via and solder bumping process. However, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are still inevitable reducing the reliability of the chips 6 . Zang et al 7 also reviewed that the formation of intermetallic compounds (IMC), voids and cracks in many well-known materials, such as SnAg, SnBi and SnZ.…”