A common requirement for all current and future TSV (Through Silicon Via) applications is the ability to handle and process thinned Silicon Wafers, usually in the range of 150m or much below. Silicon Wafers of this thickness cannot be handled without support as wafers with the standard thickness. One solution to tackle this problem is the use of wafer-support-systems (WSS), in which the thinned wafers are bonded temporarily to a carrier wafer, which gives the wafer mechanical stability. Another solution for handling are carrierless systems, in which the wafer is modified in a way that it is thin and mechanically rigid at the same time. Existing carrierless systems provide mechanical integrity for the wafer, but lack the full integration into backside processing. In this paper, we present a carrierless approach that provides mechanical stability and can be integrated into backside processing technology at the same time. We present results of a carrierless wafer with a th ickness of 60m only which has undergone a bumping process at the backside
Wafer Level Package for optical image sensor devices are known to be processed by re-routing of the bond pads to the back side of the chip, through (T) contacts located at the die edges.Bond pad back via contact wafer level packaging technology has been developed by Schott Electronic Packaging GmbH, Germany, which is proven to be with a number of advantages over the mechanically processed (T) contact Wafer Level Packages. Direct contact of the bond pads from the back side of the chip offers much shorter transmission paths to the board assemblies, thus allowing faster signal speed, efficient thermal conduction and many added advantages. Also, the new technology offers area contacts with in the seal ring / isolation boundary of the device, there-by providing much higher performance for the packaged devices. The reliability of this new WLP technology has been demonstrated by testing the same for various reliability test conditions as per JEDEC / JIS standards. This paper discusses the process technology and reliability tests / results carried out on a consumer application chip, namely image sensor device.
The Wafer level Packaging for optical image sensor devices developed by Schott Advanced Packaging utilizes a via trough contact through the Silicon by contacting the bond pads of the image sensors from the backside. Direct contact of the bond pads from the back side of the chip offers much shorter transmission paths to the board assemblies, thus providing faster signal speed, efficient thermal conduction and many added advantages [1], [2].After forming the vias by means of plasma etching [3], the electrical connection from the bottom of the via to the backside of the wafer is done by spray coating and lithography to form the redistribution layer, and prepare the wafer for bumping at a later process step.Via shape and spray coating process are the key to achieve a good quality and reliable product. This paper discusses interactions between the via shape (profile angle and profile shape) and its effect on subsequent spray coating processes. The shape of the via, and its homogeneity over the wafer, significantly affect the performance and stability of the next process steps, thus careful balancing of the via forming process and the spray coating is required.Further, the impact of via stability under production conditions on the spray coating performance is presented.
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