Vertical III–V Nanowire Device Integration on Si(100)

Abstract

We report complementary metal-oxide-semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.

III–V compound semiconductor transistors—from planar to nanowire structures

“…89 With this technique, very thin nanowires can be grown. 90 with fi ns as narrow as 30 nm and excellent characteristics have been demonstrated. 91 A summary of the state of the art of top-down fabricated InGaAs MOSFET technology for logic is presented in Figure 3c .…”

“…89 With this technique, epitaxial growth of III-V homo-and heterostructure NWs on various directions, including Si (100) and scaled NWs with a 25 nm diameter, have been demonstrated. 90 Although these wires have a very high potential for future III-V device integration on Si, the vertical device processing is more challenging.…”

Tuning growth direction of catalyst-free InAs(Sb) nanowires with indium droplets

“…For InAs nanowires changing the growth direction by droplet engineering is particularly challenging, since there is still a debate as to whether InAs nanowires grow with or without an indium droplet [14,15,35]. Catalyst-free growth of InAs nanowires along the 〈100〉 direction can be forced by using SiO 2 nanotube templates, although this strategy does not prevent the formation of stacking defects [36]. As far as we know, template and catalyst-free InAs nanowires have so far been limited to the 〈111〉B growth direction, and no in situ change of growth direction has been demonstrated yet.…”

Mechanisms of template-assisted selective epitaxy of InAs nanowires on Si

“…In addition, defects that thread on a {111} plane along a trench cannot be blocked and reach the top of the III-V layer. 9 A promising method called template-assisted selective epitaxy (TASE) was recently demonstrated, 12,13 which extends the defect-reduction concepts described above by reducing the dimensions of the elongated mask openings previously used to the small circular cross section of a nanotube, and avoiding the merging of crystallites from separate openings. In this way, threading dislocations can be avoided completely, thus allowing for local integration of III-V nanowires on Si by selective metal-organic vapor phase epitaxy (MOVPE).…”