Vertical high mobility wrap-gated inas nanowire transistor

Samuelson, Lars; Jensen, L; Wernersson, Lars‐Erik

doi:10.1109/drc.2005.1553100

Cited by 49 publications

(58 citation statements)

References 4 publications

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“…Although, InAs nanowire devices [8][9][10][11] have higher mobility than silicon based devices, the mobility in nanowires is significantly lower than that of bulk InAs [7][8][9]12 due to a variety of factors including increased electron/hole scattering rates and surface scattering mechanisms 8 . A detailed understanding of various carrier scattering mechanisms is essential to be able to improve experimental methods to build higher performance nanowire transistors in the future.…”

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confidence: 99%

Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors

Konar¹,

Mathew

Nayak

et al. 2015

Nano Lett.

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Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm 2 /V.s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than the bulk. This low sound velocity is attributed to the extended crystal defects that ubiquitously appear in these nanowires. Analyzing the temperature-dependent mobility data, we identify the key scattering mechanisms limiting the carrier transport in these nanowires. Finally, using these scattering models, we perform drift-diffusion based transport simulations of a nanowire field-effect transistor and compare the device performances with experimental measurements. Our device modeling provides insight into performance limits of InAs nanowire transistors and can be used as a predictive methodology for nanowire-based integrated circuits. KEYWORDS :InAs, nanowire, scattering, transport, field-effect transistors.Field effect transistor is the building block of integrated circuits and is key to new technologies. The aggressive scaling has pushed the silicon-based planar Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) technology to the point where transistor performances cannot be enhanced by simply reducing dimensions. For further scaling of the transistor, several 1 alternative materials (other than silicon) and device geometries have been investigated including the Fin-Field ‡ Currently with GlobalFoundaries Page 2 of 22 Effect Transistor 2,3 , Tri-gate 4 , Omega gate 5 , and Gate All-Around or wrap gate (GAA) devices 6 . Though the fabrication of GAA device geometry is much more complex in a top-down approach, GAA (wrap gate) devices offer higher performance due to its superior electrostatic controls compared to other geometries. In this work, we fabricate and evaluate the performance of high mobility InAs nanowire junctionless transistors (JLT), synthesised through a combination of a simpler bottom-up approach and conventional lithographic techniques 7 .Although, InAs nanowire devices 8-11 have higher mobility than silicon based devices, the mobility in nanowires is significantly lower than that of bulk InAs 7-9,12 due to a variety of factors including increased electron/hole scattering rates and surface scattering mechanisms 8 . A detailed understanding of various carrier scattering mechanisms is essential to be able to improve experimental methods to build higher performance nanowire transistors in the future. In this work, we develop microscopic models to understand the experimental data and the limitations of the performance of the fabricated InAs GAA junctionless InAs nanowire transistors. To do so, we first ...

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confidence: 99%

Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors

Konar¹,

Mathew

Nayak

et al. 2015

Nano Lett.

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“…Recently nanowires (NWs) have attracted attention as one of the most promising ways to combine highperformance Ⅲ-Ⅴ materials with new functionality [1][2][3][4] and existing Si technology [5,6]. An unintentional NW shell can harm device functionality by short circuiting axially designed components and by becoming a surrounding and competing recombination center [7] for charge carriers.…”

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confidence: 99%

In situ etching for total control over axial and radial nanowire growth

et al. 2010

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We report a method using in situ etching to decouple the axial from the radial nanowire growth pathway, independent of other growth parameters. Thereby a wide range of growth parameters can be explored to improve the nanowire properties without concern of tapering or excess structural defects formed during radial growth. We demonstrate the method using etching by HCl during InP nanowire growth. The improved crystal quality of etched nanowires is indicated by strongly enhanced photoluminescence as compared to reference nanowires obtained without etching.

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“…Suk et al have shown transistor data for 10-nm lateral Si wires with a full wrap gate using SiO 2 as gate dielectric [3]. In the vertical geometry, many groups are currently working with epitaxially grown nanowires [4]- [7]. An important motivation here is the possibility of growing group III-V nanowires directly on Si, as well as highly lattice-mismatched semiconductor heterostructures within a wire [8]- [10].…”

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confidence: 99%

Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

Thelander

FrobergFroberg

Rehnstedt

et al. 2008

IEEE Electron Device Lett.

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174

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Abstract-We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO 2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiO x spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiN x gate dielectrics.

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Vertical high mobility wrap-gated inas nanowire transistor

Cited by 49 publications

References 4 publications

Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors

Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors

In situ etching for total control over axial and radial nanowire growth

Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

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