Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

Abstract

Abstract-We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO 2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiO x spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiN x gate dielectrics.

Low-Frequency Noise in Vertical InAs Nanowire FETs

“…As compared to previously published data [2,9], we note a larger subthreshold slope in these devices, 120 mV/decade as compared to 80 mV/decade. This can mainly be attributed to insufficient scaling of the wire diameter for this gate length, but also a high D it .…”

“…The NW FETs are fabricated from epitaxially grown InAs nanowires with a diameter of 40 nm, grown on an <111>-B InAs substrate [2,9]. The wires are Sn-doped with a molar fraction of 3.49x10 -8 .…”

“…The nanowire geometry also offers electrostatic advantages using a wrap-around gate, providing better control of the channel potential. Good DC performance of vertical InAs NW transistors based on arrays of nanowires with 50 nm gate length has been demonstrated [2], with g m = 0.5 S/mm and a subthreshold slope of 90 mV/decade. We have recently also investigated the radio frequency (RF) performance of similar InAs nanowire FETs [3].…”

Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

“…The device exhibits enhancement mode operation (V T = 0.29 V) and combines competitive on-performance, as shown by the peak transconductance (g m,max ) of 0.64 mS μm −1 , and off-performance, characterized by the minimum sub-threshold swing (SS) of 90mV/decade at V DS = 0.5 V. For an off-current (I off ) of 100 nA μm −1 and a supply voltage of 0.5 V, the device exhibits an on-current (I on ) of 0.14 mA μm −1 . This device performance is competitive to earlier published works on vertical III-V nanowire MOSFETs [5], [11]- [13]. The good sub-threshold behavior is attributed to the fabrication method, which allows an unintentionally doped channel.…”

P-Type Phosphorus Doped ZnO Wires for Optoelectronic Applications

“…For example, studies of nanowire FETs fabricated from boron and phosphorus-doped Si nanowires have shown that the devices can exhibit performance comparable to the best reported value for planar devices made from the same materials [Cui et al, 2003]. Studies have also demonstrated the high electron mobility of epitaxial InAs nanowire FETs with a wrap-around cylindrical gate structure surrounding a nanowire [Thelander et al, 2008]. Moreover, the change in conductance of semiconductor wires as a function of gate voltage can be used to determine the conductive type of a given wire since the conductance will vary oppositely for increasing positive and negative gate voltages [Cui et al, 2003].…”