Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors

Abstract

Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm 2 /V.s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than the bulk. This low sound velocity is attributed to the extended crystal defects that ubiquitously appear in these nanowires. Analyzing the temperature-dependent mobility data, we identify the key scattering mechanisms limiting the carrier transport in these nanowires. Finally, using these scattering models, we perform drift-diffusion based transport simulations of a nanowire field-effect transistor and compare the device performances with experimental measurements. Our device modeling provides insight into performance limits of InAs nanowire transistors and can be used as a predictive methodology for nanowire-based integrated circuits. KEYWORDS :InAs, nanowire, scattering, transport, field-effect transistors.Field effect transistor is the building block of integrated circuits and is key to new technologies. The aggressive scaling has pushed the silicon-based planar Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) technology to the point where transistor performances cannot be enhanced by simply reducing dimensions. For further scaling of the transistor, several 1 alternative materials (other than silicon) and device geometries have been investigated including the Fin-Field ‡ Currently with GlobalFoundaries Page 2 of 22 Effect Transistor 2,3 , Tri-gate 4 , Omega gate 5 , and Gate All-Around or wrap gate (GAA) devices 6 . Though the fabrication of GAA device geometry is much more complex in a top-down approach, GAA (wrap gate) devices offer higher performance due to its superior electrostatic controls compared to other geometries. In this work, we fabricate and evaluate the performance of high mobility InAs nanowire junctionless transistors (JLT), synthesised through a combination of a simpler bottom-up approach and conventional lithographic techniques 7 .Although, InAs nanowire devices 8-11 have higher mobility than silicon based devices, the mobility in nanowires is significantly lower than that of bulk InAs 7-9,12 due to a variety of factors including increased electron/hole scattering rates and surface scattering mechanisms 8 . A detailed understanding of various carrier scattering mechanisms is essential to be able to improve experimental methods to build higher performance nanowire transistors in the future. In this work, we develop microscopic models to understand the experimental data and the limitations of the performance of the fabricated InAs GAA junctionless InAs nanowire transistors. To do so, we first ...

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