Verifying sequential equivalence using ATPG techniques

Abstract

In this paper we address the problem of verifying the equivalence of two sequential circuits. State-of-the-art sequential optimization techniques such as retiming and sequential redundancy removal can handle designs with up to hundreds or even thousands of flip-flops. However, the BDD-based approaches for verifying sequential equivalence can easily run into memory explosion for such designs. In an attempt to handle larger circuits, we modify test pattern-generation techniques for verification. The suggested approach utilizes the popular efficient backward-justification technique used in most sequential ATPG programs. We present several techniques to enhance the efficiency of this approach by (1) identifying equivalent flip-flop pairs using an induction-based algorithm, and (2) generalizing the idea of exploring the structural similarity between circuits to perform verification in stages. This ATPG-based framework is suitable for verifying circuits either with or without a reset state. In order to extend this approach to verify retimed circuits, we introduce a delay-compensationbased algorithm for preprocessing the circuits. The experimental results of verifying the correctness of circuits after sequential redundancy removal and retiming with up to several hundred flip-flops are presented.

Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints

“…[HCC01] An initializing sequence for C is its synchronizing sequence, and a synchronizing sequence is a ws-sequence. The converse to any of these statements is not true.…”

“…Development of sequential ATPG [HCC01] and SAT [BCC99] based verification methods made it possible to allow subcircuits with sequential logicthe subcircuits may contain internal latches. This however adds burden to equivalence verification check, not only in terms of complexity, but also in terms of semantic correctness.…”

“…The shown state encoding of the FSM in Figure 2 is such that input (l 1 =0, l 2 =1) initializes B and D. Further, for weakly synchronizable circuits, safe replaceability implies alignability [SPAB01]. And for initializable circuits, 3-valued safe replaceability implies alignability [HCC01]. Thus D is not a safe replacement or a 3-valued safe replacement of B because B and D are not alignable.…”

“…Huang et al [HCC01] point out that safe replaceability "…is more stringent (than alignability), and thus allows less flexibility for logic optimization. Furthermore, checking safe replaceability is difficult because every state of the transformed circuit needs to be examined.…”

“…But for circuits beyond the capability of BDDs, this definition cannot be checked efficiently." Therefore [HCC01] introduced 3-valued safe replaceability which is still stronger than alignability (for initializable circuits) but is easier to check, and furthermore it has excellent compositionality properties: (1) If in a large circuit every subcircuit is replaced by one of its respective 3-valued safe replacements, then the resulting circuit is 3-valued safe replacement of the original one; (2) Any initializing sequence of a circuit C initializes any of its 3-valued safe replacement circuits; and (3) Any 3-valued safe replacement of an initializable circuit C is alignable with C.…”