Sequential equivalence checking between system level and RTL descriptions

Abstract

Sequential equivalence checking between system level descriptions of designs and their Register Transfer Level (RTL) implementations is a very challenging and important problem in the context of Systems on a Chip (SoCs). We propose a technique to alleviate the complexity of the equivalence checking problem, by efficiently decomposing it using compare points. Traditionally, equivalence checking techniques use nominal or functional mapping of latches as compare points. Since we operate at a level where design descriptions are in System Level Languages or Hardware Description Languages, we leverage the information available to us at this level in deducing sequential compare points. Sequential compare points encapsulate the sequential behavior of designs and are obtained by statically analyzing the design descriptions. We decompose the design using sequential compare points and represent the design behavior at these compare points by symbolic expressions. We use a SAT solver to check the equivalence of the symbolic expressions. In order to demonstrate our technique, we present results on a non-trivial case study. We show an equivalence check between a System C description and two different Verilog RTL implementations of a Viterbi decoder, that is a component of the DRM SoC.

Tamper Evident Microprocessors

“…There has been extensive prior work on static verification of RTL level designs [68][18] [34]. Static verification involves confirming functional equivalence between a behavioral level golden model (e.g., a C program) and the RTL level design under test.…”

Formal support for untimed SystemC specifications. Application to high-level synthesis

“…In [20], the observable time windows for comparing data before and after scheduling are defined. More recently, similar techniques have been extended to SystemC by defining comparison points in the original C code of the function [21]. In all the cases, the verification methodology applies to the correct implementation of each particular function.…”

“…Once abstracted, the ForSyDe model is a 'golden' model to which any implementation can be compared. The behavioral part corresponding to the models in Figures 6 and 7, can be used as functional references for formal verification [17][18][19][20][21]. It can be extracted by symbolic simulation as proposed in [17] and [23].…”

Equivalence checking between SLM and RTL using machine learning techniques

“…With regard to formal techniques based method, Shobha Va sudevan et al [7] computed the sequential compare points and used an SAT solver to verify the points. Their method split the equivalence problem with sequential compare points.…”