Formal support for untimed SystemC specifications. Application to high-level synthesis

Abstract

SystemC lacks a well defined formal semantics for abstract specification, specifically for untimed models. This paper tackles this problem by providing the fundamentals of a framework which enables the analysis of any untimed SystemC specification under a formal meta-model. Then, the conditions for the SystemC specification to correspond with its formal metamodel are defined. As an application example, the use of the framework for high-level synthesis verification is shown.

Formal foundations for MARTE-SystemC interoperability

“…Furthermore, a more flexible interpretation is feasible to support formalization of abstract models, such as in [23] where untimed SystemC models are formalized. Similarly, in [24], ForSyDe was used to reflect the abstract executive semantics of high-level PIM MARTE models, whose SystemC mapping was defined in [25].…”

“…Using ForSyDe as the linking formalism enables all its potential applications. As a first example of this potential, in [23], an application of the formalism, to validate implementation refinement is shown. Furthermore, ForSyDe has the necessary elements to yield understandable and coherent semantics for heterogeneous specifications.…”

“…This requires a coherent integration of the considerations done in [25] and in [23] for MARTE and SystemC formalization, respectively, in order to state the possibilities and limits of the MARTE/SystemC relationship.…”

“…When the semantic of the MARTE CommunicationMedia, and its corresponding SystemC communication scheme (usually, a SystemC channel), is semantically simple [23], then they share a ForSyDe representation as a set of ForSyDe signals, reflecting the transfer of values (in general bi-directional) among the communicated ConcurrencyResources/SystemC processes. Simple communication semantics causes an alteration neither in the values transferred, nor in their ordering, nor an injection, nor a loss of data in the sequence.…”