Use of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology

Abstract

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 °C, we measured an active dopant concentration of about 2.1 × 10 20 cm -3 and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1-4 × 10 13 cm -2 ) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values.

Liquid-Phase Monolayer Doping of InGaAs with Si-, S-, and Sn-Containing Organic Molecular Layers

“…However, the junction depths are quite deep highlighting the need for more advanced annealing techniques with faster ramp up and ramp down rates in addition to emerging techniques such as flashlamp and laser annealing. 51−54…”

“…Despite the difficulty in characterizing the Si-doped samples, we have shown that it is possible to co-dope InGaAs with S and Si simultaneously using liquid-phase, ambient pressure surface chemistry. However, the junction depths are quite deep highlighting the need for more advanced annealing techniques with faster ramp up and ramp down rates in addition to emerging techniques such as flashlamp and laser annealing. − …”

Improved physical models for advanced silicon device processing

“…Classical standard doping techniques like ion implantation may not be suitable for FinFET devices because of the 3D geometry. Several solutions to incorporate dopants in the fin are being explored such as tilted ion implantation [23,153,158], plasma doping [159][160][161][162] or vapor phase doping [163]. Among them, tilted ion implantation remains a strong candidate to introduce dopants into the fin, as it is a conventional and well established technique, although it suffers from specific issues that arise from the particular geometry of these devices.…”

Boron Delta-Doping Dependence on Si/SiGe Resonant Interband Tunneling Diodes Grown by Chemical Vapor Deposition

“…Vapor-phase doping technique is utilized to achieve the p and n δ-doping spike, wherein the dopant atoms are deposited on the wafer by thermal decomposition of diborane (B 2 H 6 ) and phosphine (PH 3 ), respectively [24], [25]. A set of four wafers were grown with the boron flow varied over a factor of 6 to modify the boron content in the bottom δ-doped layer.…”