Universal theory of workfunctions at metal/Hf-based high-k dielectrics interfaces - guiding principles for gate metal selection

Shiraishi, Kenji; Akasaka, Y.; Miyazaki, Seiichi; Nakayama, Takashi; Nakaoka, T.; Nakamura, Genji; Torii, Kazuyoshi; Furutou, H.; Ohta, Akio; Ahmet, Parhat; Ohmori, Kenji; Watanabe, Heiji; Chikyow, T.; Green, M.L.; Nara, Yasuo; Yamada, Keiichi

doi:10.1109/iedm.2005.1609260

Cited by 22 publications

(21 citation statements)

References 3 publications

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“…In order to elucidate the anomalous negative shift observed in the W-rich region, we employed the GCNL theory that describes charge transfer in metallic and high-k dielectric films in contact. 17 In the previous charge neutrality level ͑CNL͒ model, 15,18 the charge neutrality level is determined by the high-k dielectric film itself. On the other hand, in the GCNL theory, the bonding configuration at the metal high-k interface and the density of states of the metal are essential for the determination of the generalized charge neutrality level on which the effective WF of metals depends.…”

Section: Resultsmentioning

confidence: 99%

Influences of annealing in reducing and oxidizing ambients on flatband voltage properties of HfO2 gate stack structures

Ohmori

Ahmet

Yoshitake

et al. 2007

Journal of Applied Physics

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We have applied a combinatorial technique to fabricate work function ͑WF͒ tuned Pt-W alloy films and used the films as metal electrodes for HfO 2 / SiO 2 / Si capacitors. As the ratio, R Pt , of Pt to W changes from 0 to 1, the WF value varies continuously from 4.7 to 5.5 eV. This tunability enables us to systematically investigate the effect of WF variation on electrical properties. After a forming gas annealing process, the values of flatband voltage ͑V fb ͒ from capacitance-voltage properties are almost constant, regardless of the WF variation, because of oxygen vacancy formation that results in Fermi level pinning. On additional oxidizing gas annealing ͑OGA͒, the effect of WF value on V fb becomes dominant. However, the difference in V fb between W and Pt is 0.34 V, which is much smaller than the observed WF difference of 0.8 eV. We attribute this phenomenon to the lowering of the effective WF due to an electric dipole, induced by oxygen vacancy formation at the metal/ HfO 2 interface. Moreover, a decrease in V fb in W-rich regions was observed following the OGA, suggesting the formation of a W-O bond at the interface. These results clearly indicate that the control of bonding states at the metal/HfO 2 interfaces on an atomic scale is essential for the realization of a combination of metal and high-k dielectric films in future complementary metal-oxide-semiconductor devices.

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Section: Resultsmentioning

confidence: 99%

Influences of annealing in reducing and oxidizing ambients on flatband voltage properties of HfO2 gate stack structures

Ohmori

Ahmet

Yoshitake

et al. 2007

Journal of Applied Physics

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“…A second effect that may contribute to a reduction of the vacancy formation energy relates to the electronic structure of the vacancy and the alignment of its energy levels with respect to the Fermi level in the contacts, allowing for electron transfer from the vacancy to the Si and/or to the metal contacts. This process will further lower the overall energy for vacancy formation (for details, see [13,14]). Within this scenario, the same defect is deemed responsible for both the V t instability and the SILC generation.…”

Section: Defect Creation and Correlation Between Silc Formation Anmentioning

confidence: 99%

Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Cartier

Kerber

2009

2009 IEEE International Reliability Physics Symposium

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The stress-induced leakage current (SILC) in nFETs with SiO 2 /HfO 2 /TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias temperature stress at high temperatures and at high gate stress voltage. It is shown that strong defect creation in the HfO 2 causes a linear increase of the SILC with stress time. The SILC generation is found to be thermally activated with an activation energy, E a ~ 1 eV. In addition, the SILC formation exhibits a strong correlation with the threshold voltage (V t ) instability ΔI g /I g ~ dV t 3 . Both degradation phenomena show a strong hysteretic behavior with gate bias; the SILC and V t -degradation are observed to be substantially reduced by applying a negative gate bias after stress. All these observations may be rationalized in terms of charge trapping in shallow HfO 2 defects -such as oxygen vacancy -and by the generation of new shallow defects during stress. The defect generation process has a low activation energy, likely because of thin-film effects. Therefore, the SILC and the V t instability are large under accelerated TDDB test conditions. It is also shown that the observed low activation energy in combination with the reversibility of the SILC has important implications for dielectric breakdown detection in dual-dielectric gate stacks.

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“…Although the interfacial layer can suppress Fermi-pinning, the increase in the effective oxide thickness is adverse to device scaling. 29) The È m,eff of a P-type poly-Si gate on HfO 2 is also shown in Fig. 6.…”

Section: Thermal Stability Of the Fully-silicided Nisi Gatementioning

confidence: 99%

Investigation of NiSi Fully-Silicided Gate on SiO₂ and HfO₂ for Applications in Metal–Oxide–Semiconductor Field-Effect Transistors

Huang¹,

Tsui²

2006

Jpn. J. Appl. Phys.

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Effective work function modulation (È m,eff ) and the thermal/electrical stability of NiSi fully-silicided (FUSI) gates on SiO 2 and HfO 2 are investigated. A new method, implant-to-silicide, differing from the pre-doped method, is used to realize È m,eff adjustments. The È m,eff of NiSi FUSI gates on SiO 2 can be tuned by incorporating BF 2 þ or P þ dopants after silicidation. Nevertheless, the Fermi-pinning effect was observed in the NiSi/HfO 2 gate which limits the È m,eff adjustment. A thin SiO 2 interfacial layer can reduce the Fermi-pinning effect. A NiSi FUSI gate on SiO 2 is thermally stable up to 600 C. The thermal stress and impurity diffusion after a prolonged 600 C annealing degraded the oxide integration. The temperature of the post-silicidation process should be as low as possible to lessen the thermal stress and impurity diffusion.

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Universal theory of workfunctions at metal/Hf-based high-k dielectrics interfaces - guiding principles for gate metal selection

Cited by 22 publications

References 3 publications

Influences of annealing in reducing and oxidizing ambients on flatband voltage properties of HfO2 gate stack structures

Influences of annealing in reducing and oxidizing ambients on flatband voltage properties of HfO2 gate stack structures

Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Investigation of NiSi Fully-Silicided Gate on SiO₂ and HfO₂ for Applications in Metal–Oxide–Semiconductor Field-Effect Transistors

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Universal theory of workfunctions at metal/Hf-based high-k dielectrics interfaces - guiding principles for gate metal selection

Cited by 22 publications

References 3 publications

Influences of annealing in reducing and oxidizing ambients on flatband voltage properties of HfO2 gate stack structures

Influences of annealing in reducing and oxidizing ambients on flatband voltage properties of HfO2 gate stack structures

Stress-induced leakage current and defect generation in nFETs with HfO<inf>2</inf>/TiN gate stacks during positive-bias temperature stress

Investigation of NiSi Fully-Silicided Gate on SiO2 and HfO2 for Applications in Metal–Oxide–Semiconductor Field-Effect Transistors

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Investigation of NiSi Fully-Silicided Gate on SiO₂ and HfO₂ for Applications in Metal–Oxide–Semiconductor Field-Effect Transistors