Understanding and minimizing ground bounce during mode transition of power gating structures

Kim, Suhwan; Kosonocky, Stephen; Knebel, D.R.

doi:10.1145/871506.871515

Cited by 124 publications

(76 citation statements)

References 12 publications

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“…These switches are parallel-connected between the mesh of the chip's true VDD (or ground) and the mesh of the gated domain's virtual VDD (or virtual ground). This power-switch fabric, also called a distributed sleep transistor network (DSTN [2]), along withits control scheme significantly affect the characteristics of the MTCMOS design [1]- [13], [19]- [22], and thus need to be carefully designed.…”

Section: Literature Surveymentioning

confidence: 99%

Novel power –up sequence control for MTCMOS designs

Nagarjuna¹,

Prashanth²

2014

International Journal of Advanced Research in Computer and Comm

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Power gating is effective for reducing standby leakage power as multi-threshold CMOS (MTCMOS) designs have become popular in the industry. However, a large inrush current and dynamic IR drop may occur when a circuit domain is powered up with MTCMOS switches. This could in turn lead to improper circuit operation. We propose a novel framework for generating a proper power-up sequence of the switches to control the inrush current of a powergated domain while minimizing the power-up time and reducing the dynamic IR drop of the active domains. We also propose a configurable domino-delay circuit for implementing the sequence. Experimental results based on state-ofthe-art industrial designs demonstrate the effectiveness of the proposed framework in limiting the inrush current, minimizing the power-up time, and reducing the dynamic IR drop. Results further confirm the efficiency of the framework in handling large-scale designs with more than 40 K power switches and 50 M transistors.

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Section: Literature Surveymentioning

confidence: 99%

Novel power –up sequence control for MTCMOS designs

Nagarjuna¹,

Prashanth²

2014

International Journal of Advanced Research in Computer and Comm

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“…Kim et al proposed reducing glitches on the ground and power rails due to inrush current by dynamically controlling the gate-to-source voltage (Vgs) of sleep transistors [14]. They also proposed daisy-chaining the wakeup of the sleep transistors in a chain of size-increasing sleep transistors.…”

Section: Previous Workmentioning

confidence: 99%

“…The above mentioned solutions in [14,10,22,6] are suitable for handling inrush current for designs where the functional blocks are known beforehand. Unlike ASICs, FPGAs are configurable, and they need a solution that is suitable to a wide range of applications.…”

Section: Previous Workmentioning

confidence: 99%

A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs

Bsoul

Wilton

2012

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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A dynamically-controlled power-gated (DCPG) FPGA architecture has recently been proposed to reduce static energy dissipation during idle periods. During a power mode transition from an off state to on state, the wakeup current drawn from power supplies causes a voltage droop on the power distribution network of a device. If not handled appropriately, this current and the associated voltage droop could cause malfunction of the design and/or the device. In DCPG FPGAs, the amount of wakeup current is not known beforehand as the structures of power-gated modules are application dependent; thus, a configurable solution is required to handle wakeup current. In this paper we propose a programmable wakeup architecture for DCPG FPGAs. The proposed solution has two levels: a fixed intra-region level and a configurable inter-region level. The architecture ensures that a power-gated module can be turned on such that the wakeup current constraints are not violated. We study the area and power overheads of the proposed solution. Our results show that the area overhead of the proposed inrush current limiting architecture is less than 2% for a power gating region of size 3x3 or 4x4 tiles, and the leakage power saved is more than 85% in a region of size 4x4 tiles.

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“…The proposed techniques include sleep transistor designs [3,4], decoupling capacitor insertion [5], and P/G noise-aware floorplanning [1,2,6]. Recently, power gating sequence scheduling [7][8][9] in a block or several blocks were proposed to tradeoff wake-up time for P/G noise reduction.…”

Section: Introductionmentioning

confidence: 99%

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise

Liu

Wang

et al. 2009

2009 IEEE Computer Society Annual Symposium on VLSI

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Power gating induced power/ground (P/G) noise is a major reliability problem facing by low power MPSoCs using power gating techniques. Powering on and off a processing unit in MPSoCs will induce large P/G noise and can cause timing divergence and even functional errors in surrounding processing units. P/G noise is different from thermal or energy which is an accumulative effect. The noise level should be predicted and victim circuits should be protected before the noise is induced. Hence, the power gating-aware scheduling problem with the consideration of P/G noise should be solved using an on-line method considering the run-time variation of tasks' execution time. In this paper, we formulate an on-line task scheduling problem with the consideration of P/G noise based on our detailed P/G noise analysis platform for MPSoC. An efficient on-line Greedy Heuristic (GH) algorithm that adapts well to real-time variations is proposed to reduce noise protection penalty and improve MPSoC performance. Our experiments show that the algorithm can achieve on average 26% performance improvement together with on average 73% noise protection penalty saving compared with the conservative stop-go method. We also compare our technique with a twostep solution that computes a static schedule at compile time and make adjustment on the schedule according to runtime variations. For benchmark with larger task number, GH method achieves impressive performance improvement comparing with the two-step solution.

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Understanding and minimizing ground bounce during mode transition of power gating structures

Cited by 124 publications

References 12 publications

Novel power –up sequence control for MTCMOS designs

Novel power –up sequence control for MTCMOS designs

A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise

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