Ultra-shallow source/drain junctions for nanoscale CMOS using selective silicon-germanium technology

Öztürk, Mehmet C.; Pesovic, N.; Kang, I.; Liu, J.; Mo, Hongxiang; Gannavaram, S.

doi:10.1109/iwjt.2001.993832

Cited by 4 publications

(2 citation statements)

References 4 publications

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“…An in-situ SiGe doping may have been performed during its epitaxial growth resulting in a higher boron concentration in SiGe. This is further enhanced by the high level of boron activation in SiGe reported by Ozturk [3]. Figure 5 shows a SEM cross-section of two adjacent PMOS transistors.…”

Section: Carrier Profiles In Boron Doped Silge1mentioning

confidence: 89%

2D carrier mapping in Si/sub 1-x/Ge/sub x/ source/drain regions of PMOSFETs used in a production device by scanning capacitance microscopy

Nxumalo¹,

Wintgens²,

Haythornthwaite³

et al. 2005

Extended Abstracts of the Fifth International Workshop on Junction Technology

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This article presents the results of a 2D carrier profile analysis of a finished 90 nm MPU with strained silicon by scanning capacitance microscopy (SCM). First, we show that the carrier concentration measurement dynamic range of SCM spans 1014_1020 cm-3. Then we present results that demonstrate p-n junction delineation on PMOS transistor with embedded SiGe in the source/drain regions. A big difference ofcarrier concentration in SiGe with respect to the surrounding silicon tends to indicate that in-situ boron doping was employed during SiGe S/D growth. We also report observed anomalous lateral "overgrowth" of SiGe overfield oxide that may compromise manufacturing yield.

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Section: Carrier Profiles In Boron Doped Silge1mentioning

confidence: 89%

2D carrier mapping in Si/sub 1-x/Ge/sub x/ source/drain regions of PMOSFETs used in a production device by scanning capacitance microscopy

Nxumalo¹,

Wintgens²,

Haythornthwaite³

et al. 2005

Extended Abstracts of the Fifth International Workshop on Junction Technology

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show abstract

“…D URING the past decade [1]- [12], embedded silicongermanium (e-SiGe) has been widely utilized in modern CMOS technology with the aim to enhance pMOSFET performance. Not only can hole mobility benefit from lattice-induced mechanical strain but also source/drain series resistance (R sd ) can be reduced with optimization of in situ doping techniques.…”

Section: Introductionmentioning

confidence: 99%

An Extreme Surface Proximity Push for Embedded SiGe in pMOSFETs Featuring Self-Aligned Silicon Reflow

Lin

Chen

et al. 2010

IEEE Electron Device Lett.

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This letter proposes a novel process to modulate the distance, or proximity, between the tip of embedded silicongermanium (e-SiGe) and the channel region in pMOSFETs. Traditionally, sophisticated etching treatment is adopted in a spacer structure; however, process-induced variation in the e-SiGe proximity may lead to serious variation in pMOSFET performance. In this letter, an extremely close proximity is achieved using selfaligned silicon reflow (SASR) in hydrogen ambient. As opposed to conventional approaches which have e-SiGe proximity determined by spacer width, the tip of e-SiGe with SASR can be positioned flush with the gate edge, as corroborated by both the TEM analyses and TCAD simulation. A significant improvement in pMOSFET performance is also measured.

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A Logic Nanotechnology Featuring Strained-Silicon

Thompson

Armstrong

Auth

et al. 2004

IEEE Electron Device Lett.

485

190

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Ultra-shallow source/drain junctions for nanoscale CMOS using selective silicon-germanium technology

Cited by 4 publications

References 4 publications

2D carrier mapping in Si/sub 1-x/Ge/sub x/ source/drain regions of PMOSFETs used in a production device by scanning capacitance microscopy

2D carrier mapping in Si/sub 1-x/Ge/sub x/ source/drain regions of PMOSFETs used in a production device by scanning capacitance microscopy

An Extreme Surface Proximity Push for Embedded SiGe in pMOSFETs Featuring Self-Aligned Silicon Reflow

A Logic Nanotechnology Featuring Strained-Silicon

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