Ultra-Low Voltage Split-Data-Aware Embedded SRAM for Mobile Video Applications

Gong, Na; Jiang, Shanshan; Challapalli, A.; Fernandes, Sherwin; Sridhar, R.

doi:10.1109/tcsii.2012.2231018

Cited by 35 publications

(25 citation statements)

References 8 publications

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“…The overall bitline power consumption is data dependent. Many data-aware cells have been reported in the literature to control the bitline power consumption [98][99][100][101][102]. Chiu et al [103] have proposed 8T single-ended subthreshold SRAM with cross-point data-aware write operation.…”

Section: Data-aware Power-efficient Sram Cellmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.

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Section: Data-aware Power-efficient Sram Cellmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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“…Kwon et al propose Heterogeneous SRAM with varying cell sizes to trade reliability for leakage power savings [20]. Gong et al introduce an ultralow voltage split-data-aware 10T and 8T SRAM for the same goal [13]. Chang el al.…”

Section: Related Workmentioning

confidence: 99%

“…This heterogeneity is realized by controlling transistor sizing [20], operating voltage [10], or number of transistors per cell [8,13]. By allocating higher-order bits to more reliable segments power consumption can be significantly reduced with an (almost) undetectable degradation of the video quality.…”

Section: Introductionmentioning

confidence: 99%

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eDRAM-based tiered-reliability memory with applications to low-power frame buffers

Cho

Lee

et al. 2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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Embedded DRAM (eDRAM) is becoming more and more popular as a low-cost alternative to on-chip SRAM. eDRAM is particularly attractive for frame buffers in video applications with ever increasing screen resolutions. However, eDRAM suffers short retention time and high refresh power, which prevents its widespread adoption. To save the refresh power of eDRAM-based frame buffers, we propose TieredReliability Memory (TRM), where the frame buffer is divided into multiple segments with different refresh periods and hence different error rates. By allocating most-significant bits to the most reliable segment, our four-tier TRM reduces refresh power by 48% without degrading user experience.

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“…1, a low power design for SRAM can be achieved through decreasing one or more of the above four parameters simultaneously. The technique of voltage scaling down in [9] can be used to get a low power design due to its square-effect in Eq. 1, however, this approach will generate performance decline as an overhead in order to guarantee no timing-error during the read and write operations.…”

Section: Introductionmentioning

confidence: 99%

A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing

Yang

Huang

Chen

et al. 2016

IEICE Electron. Express

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By adopting the human visual system property, a priority-based selective bit dropping strategy to reduce DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) power consumption is presented in this paper. The tradeoff between power consumption and output quality is explored as well. During the data flow in image processing, the original image data are first processed with our proposed strategy, from which the number of bit-'1' in lower part of each pixel is reduced. Then the approximate data are pushed into the DRAM and SRAM for further computation, where the refresh power consumption for DRAM is reduced due to the less bit-'1' in each data and the write power consumption for SRAM is also reduced due to the lower switch probability in write operation. The proposed strategy has been realized with digital logic circuits and the approximate image data are processed by the Discrete Cosine Transform (DCT) in simulation. The results show that 27.7% refresh power reduction on average for DRAM can be achieved and the SRAM also obtained 21.7% write power reduction with negligible overhead. As for the final output quality of the images, only 1.01 dB losses for Peak-Signal-Noise-Ratio (PSNR) is presented (about 3% lower than accurate processing) after the DCT processing.

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Ultra-Low Voltage Split-Data-Aware Embedded SRAM for Mobile Video Applications

Cited by 35 publications

References 8 publications

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

eDRAM-based tiered-reliability memory with applications to low-power frame buffers

A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing

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