A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing

Yang, Xinghua; Huang, Nanyang; Chen, Yuanchang; Qiao, Fei; Yang, Huazhong

doi:10.1587/elex.13.20160990

Cited by 3 publications

(3 citation statements)

References 15 publications

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“…The approach showed to be interesting since cells can be completely powered off or even omitted. 4,25,26 The dropped bitlines correspond to a certain number of LSBs in each word, since the impact of errors is exponentially lower for smaller bit weights. This can be paired with the consideration that in many applications, such as machine learning, big data and multimedia, the quality is defined essentially by the MSBs.…”

Section: Bit Dropping Fault Modelmentioning

confidence: 99%

“…The technique is independent of technology and can be applied to both SRAM and DRAM memory circuits. 25 For SRAM memory cells the precharge circuit of the selected LSBs is disabled during read and write operations. This approach is quite different from the traditional dual V DD scheme where the supply voltage of both precharge circuits and bitcells of the selected columns is reduced to a lower value.…”

Section: Bit Dropping Fault Modelmentioning

confidence: 99%

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Full System Emulation of Approximate Memory Platforms with AppropinQuo

Stazi¹,

Mastrandrea²,

Olivieri³

et al. 2019

Journal of Low Power Electronics

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In this work we present an emulation framework for hardware platforms provided with approximate memory units, called AppropinQuo. The specific characteristic of AppropinQuo is to reveal the effects, on the hardware platform and on software, of errors introduced by approximate memory circuits and architectures. The emulator allows to execute software code without any modification with respect to the target physical board, since it includes the CPU, the memory hierarchy and the peripherals, capturing as well software-hardware interactions and faults due to approximate memory units. The final scope is reproducing the effects of errors generated by approximate memory circuits, allowing to evaluate the impact (quality degradation) on the output produced by the software. In fact, output quality is related to error rate, but their relationship strongly depends on the application, the implementation and its data representation on physical memory. The idea behind approximate memory circuits and approximate computing in general is to trade off energy consumption at the expense of computational accuracy and degradation of output quality. Memory is accounted for a large part of total power consumption in advanced architectures and it is supposed to increase as new memory hungry applications migrate toward the implementation on embedded systems (embedded machine learning, high definition video codecs, etc.). By relaxing design constraints regarding error probability on bit cells, researchers have proposed techniques that significantly reduce memory energy consumption. These techniques, which can be accounted in the general topic of approximate memory design, are implemented at circuit or architecture level, and are specific to the memory technology (i.e., SRAM or DRAM memories). However, the level of acceptable output degradation is the final metric that must be used to assess if, and to what extent, an approximate memory technique can be introduced. Our emulator allows to run actual applications as on the physical platform, to expose the effects of specific approximate memory circuits and architectures on output quality and to vary their parameters (e.g., error rate, number of affected bits, etc.). By exploring the approximate memory design space and its effects on the output of a software application, it is possible to characterize the application behavior, as a step toward the determination of the trade-off between saved energy and output quality (energy-quality tradeoff).

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Section: Bit Dropping Fault Modelmentioning

confidence: 99%

Section: Bit Dropping Fault Modelmentioning

confidence: 99%

Full System Emulation of Approximate Memory Platforms with AppropinQuo

Stazi¹,

Mastrandrea²,

Olivieri³

et al. 2019

Journal of Low Power Electronics

View full text Add to dashboard Cite

show abstract

“…It offers an efficient solution for the memory's power/thermal problems based on CMOS building blocks and circuits. Adaptive body bias technique is efficient for controlling the power dissipation and temperatures of memory systems for both SRAM and DRAM units [3].…”

Section: Introductionmentioning

confidence: 99%

Power and thermal management in SRAM and DRAM using adaptive body biasing technique

HamaAli

Sulaiman

İbrahim

2019

IEICE Electron. Express

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Low power and thermal design techniques are more advantageous for high-performance memory cells. Body bias is an adaptive technique used for power and thermal management in memory systems. It offers an efficient solution for the memory's power and thermal problems. In this study, a thermal management controller is presented as a complete hardware tuning loop. The controller is applied on both Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) units that actively monitors and controls the temperature via the power dissipation control in both memory types. The proposed combined circuits within the tuning loop are able to reduce the high power and temperatures, and dragging it around safe limits to avoid chip hardware damages. Results confirm that, the power dissipation of 6T SRAM cell is reduced by 9.77%, while the power of 1T1C DRAM cell is reduced by 8.50%. Thermal reduction was in the range of (5°C-10°C) per each body bias step voltage.

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Cross-Level Design of Approximate Computing for Continuous Perception System

Liu

Yang

et al. 2022

Approximate Computing

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A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing

Cited by 3 publications

References 15 publications

Full System Emulation of Approximate Memory Platforms with AppropinQuo

Full System Emulation of Approximate Memory Platforms with AppropinQuo

Power and thermal management in SRAM and DRAM using adaptive body biasing technique

Cross-Level Design of Approximate Computing for Continuous Perception System

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