Ultra high density logic designs using transistor-level monolithic 3D integration

Abstract

Recent innovations in monolithic 3D technology enable much higher-density vertical connections than today's through-siliconvia (TSV)-based technology. In this paper, we investigate the benefits and challenges of monolithic 3D integration technology for ultra high-density logic designs. Based on our layout experiments, we compare important design metrics such as area, wirelength, timing, and power consumption of monolithic 3D designs with the traditional 2D designs. We also explore various interconnect options for monolithic 3D ICs that improve design density and quality. Depending on the interconnect settings of monolithic 3D ICs and the benchmark circuit characteristics, we observe that our two-tier monolithic 3D design provides up to 40% reduced footprint, 27.7% shorter wirelength, 39.7% faster operation, and 9.7% lower power consumption over the 2D counterpart.

TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs

“…Since the size of a monolithic interdie via is comparable to that of a local via, monolithic 3-D integration provides a new design option, which is designing and using 3-D standard cells [29]. 3-D standard cells are 30% to 40% smaller than 2-D standard cells, so we need to change the value of L gate to predict the quality of monolithic 3-D ICs.…”

“…An issue in the prediction of the quality of monolithic 3-D ICs, however, is routing congestion. According to [29], monolithic 3-D ICs have serious routing congestion problems, so we should increase the die area, use more routing layers, or reduce the wire width to minimize the routing congestion. Increasing the die area is modeled by increasing the footprint area of a 3-D chip (A 3−DFP ) in [1].…”

Design challenges and solutions for ultra-high-density monolithic 3D ICs

“…In this design style, each standard cell is redesigned such that its PMOS and NMOS are on different tiers [3], [4], [5]. As in the case of SRAM, the advantage of doing this is that the PMOS and NMOS can be optimized separately.…”

Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology

“…The increasing wire delays is one of the major impediments for performance improvement [Xie et al 2010] under the same power budget. Monolithic 3D offers an opportunity to continue the performance improvements and power saving by reducing the interconnect distance, which makes it one of the most promising technology for circuit scaling [Lee et al 2012].…”