TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs

Abstract

3-D integrated circuits (3-D ICs) are expected to have shorter wirelength, better performance, and less power consumption than 2-D ICs. These benefits come from die stacking and use of through-silicon vias (TSVs) fabricated for interconnections across dies. However, the use of TSVs has several negative impacts such as area and capacitance overhead. To predict the quality of 3-D ICs more accurately, TSV-aware 3-D wirelength distribution models considering the negative impacts were developed. In this paper, we apply an optimal buffer insertion algorithm to the TSV-aware 3-D wirelength distribution models and present various prediction results on wirelength, delay, and power consumption of 3-D ICs. We also apply the framework to 2-D and 3-D ICs built with various combinations of process and TSV technologies and predict the quality of today and future 3-D ICs. Index Terms-3-D IC, interconnect prediction, through-silicon via (TSV), wirelength distribution.

Clock skew reduction for stacked chips using multiple source buffers

“…A contact resistance of 100 Ω was used in [22]. Moreover, the resistances of tungsten and ploy-Si are more than the resistance of Cu [23,24]. In consideration of these factors, we used 1 Ω and 10 Ω as the contact resistance.…”

Physical Design Automation for 3D Chip Stacks

“…However, note that the HPWL should be determined step-wise in 3D chips to achieve reasonable accuracy; all partial nets (i.e., net segments encapsulated in separate dies/layers) are to be independently estimated and subsequently summed up [8]. Kim et al [74] proposed an interconnect model which is TSV-aware and emulates optimal buffer insertion. Thus, this model helps to efficiently evaluate wirelength, delay and power consumption of 3D chips.…”

3DIC benefit estimation and implementation guidance from 2DIC implementation

“…They report that for realistic sizes of VIs, the benefits will always be negative (-2% on average). Kim et al [10] [12] use Rent's rule to predict wirelength distributions in 3DICs with two or more dies as well as by varying the number of VIs.The authors also derive analytical models to estimate 3D power when heights and widths of VIs, and the number of buffers inserted into the netlist, are varied. However, these models cannot predict the power benefit with 3D implementation when a 2D implementation already exists, since the models do not account for IC implementation details such as floorplan context, technology libraries, signoff corners and constraints.…”