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Stacking multiple device strata can improve system performance of a microprocessor (μP) by reducing interconnect length. This enables latency improvement, power reduction, and improved memory bandwidth. In this paper we review some of our recent design analysis and process results which quantitatively show the benefits of stacking applied to μPs.We report on two applications for stacking which take advantage of reduced wire length- “logic+logic” stacking and “logic+memory” stacking. In addition to optimizing minimum wire length, we considered carefully the thermal ramifications of the new designs. For the logic+memory application, we considered the case of reducing off-die wiring by stacking a DRAM cache (32 to 64MB) onto a high performance μP. Simulations showed 3x reduced off-die bandwidth, Cycles Per Memory Access (CPMA) reduction of 13%, and a 66% average bus power reduction. For logic+logic applications, we considered a high performance μP where the unit blocks were repartitioned into two strata. For this case, simulations showed that stacking can simultaneously reduce power by 15% while increasing performance by 15% with a minor 14° C increase in peak temperature compared to the planar design. Using voltage scaling, this translates to 34% power reduction and 8% performance improvement with no temperature increase. We found that these results can be further improved by a secondary splitting of the individual blocks. As an example, we split a 32KB first level data cache resulting in 25% power reduction, 10% latency reduction, and 20% area reduction.We also discuss the fabrication of stacked structures with two complimentary process flows. In one case, we developed a 300mm wafer stacking process using Cu-Cu bonding, wafer thinning, and through-silicon vias (TSVs). This technology provides reliable bonding with non-detectable bonding-interface resistance and inter-strata via pitch below 8μm. We investigated the impact of this wafer stacking process to the transistor and interconnect layers built using a 65nm strained-Si/Cu-Low-K process technology and found no impact to either discrete N- and P-MOS devices or to thin 4Mb SRAMs. We verified fully functional SRAMs on thinned wafers with thicknesses down to 5μm. Although wafer stacking leads itself well to tight-pitch same-die-size stacking, die stacking enables integration of different size dies and includes opportunity to improve yield by stacking known good dies. We demonstrated a die stack process flow with 75μm thinned die, TSV, and inter-strata via pitch below 100μm. We also found negligible impact to transistors using this process flow. Multiple stacks of up to seven 75μm thin dies with TSVs were fabricated and tested. Prospects for high volume integration of 3D into μPs are discussed.

Recent innovations in monolithic 3D technology enable much higher-density vertical connections than today's through-siliconvia (TSV)-based technology. In this paper, we investigate the benefits and challenges of monolithic 3D integration technology for ultra high-density logic designs. Based on our layout experiments, we compare important design metrics such as area, wirelength, timing, and power consumption of monolithic 3D designs with the traditional 2D designs. We also explore various interconnect options for monolithic 3D ICs that improve design density and quality. Depending on the interconnect settings of monolithic 3D ICs and the benchmark circuit characteristics, we observe that our two-tier monolithic 3D design provides up to 40% reduced footprint, 27.7% shorter wirelength, 39.7% faster operation, and 9.7% lower power consumption over the 2D counterpart.

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This study reports on the preparation of cobalt doped zinc oxide (Co:ZnO) films via pulsed electron beam ablation (PEBA) from a single target containing 20 w% Co on sapphire (0001) and silicon (100) substrates. The films have been deposited at various temperatures (350оC, 400оC, 450оC) and pulse frequencies (2 Hz, 4 Hz), under a background argon (Ar) pressure of about 3 mtorr, and an accelerating voltage of 14 kV. The surface morphology has been examined by atomic force microscopy (AFM) and scanning electron microscopy (SEM). According to SEM analysis, the films consist of nano-globules whose size is in the range of 80-178 nm. Energy dispersive x-ray spectroscopy (EDX) reveals that deposition is congruent and the prepared films contain ∼20±5 w% cobalt. It has been found that the nano-globules in the deposited films are cobalt-rich zones containing ∼70 w% Co. From x-ray photoelectron spectroscopy (XPS) analysis, Co 2p3/2 peaks indicate that the deposited films contain CoO (binding energy = 780.5 eV) as well as metallic Co (binding energy = 778.1-778.5 eV). X-ray diffraction (XRD) analysis supports the presence of metallic Co hcp phase (2ϴ = 44.47° and 47.43°) in the films.

Understanding thermal conduction in interlayer dielectrics (ILDs) is important for the optimal design of interconnect layers in backend semiconductor processing for future highperformance nano-scale devices. Reduced thermal conductivity of porous ILDs for example can adversely affect the temperature rise in the embedded metal lines leading to un-desirable reliability issues and design constraints. In this paper, we report results of our theoretical and experimental investigation of thermal transport in amorphous and porous dielectrics. A phononhopping model has been adapted to calculate the thermal conductivity in disordered materials. The value of hopping integral has been calculated by comparing the modeling results with experimental data for various amorphous and porous materials. The model shows reasonable agreement with experimental data for various amorphous materials including SiO 2 and other glasses over a wide temperature range from 50K -300K. The model suggests that the hopping of localized high frequency phonons is a dominant thermal transport mechanism in such material systems.