Two-parallel Reed-Solomon based FEC architecture for optical communications

Lee, Seungbeom; Choi, Chang Soo; Lee, Hanho

doi:10.1587/elex.5.374

Cited by 24 publications

(16 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…By using the S-DCME to implement the KES block, the proposed architecture has lower hardware complexity compared with Decoder blocks Proposed three-parallel. Three-parallel [13] Two-parallel [18] Serial [16] SC block n/3 n/3 n/2 n KES block 2t 10t 10t (b) Three-parallel architecture using S-DCME Figure 10 Comparison of timing chart between threeparallel architectures using pDCME and S-DCME.…”

Section: Resultsmentioning

confidence: 99%

Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications

Lee

Sunwoo

2010

J Sign Process Syst

View full text Add to dashboard Cite

This paper proposes a high-speed and areaefficient three-parallel Reed-Solomon (RS) decoder using the simplified degree computationless modified Euclid (S-DCME) algorithm for the key equation solver (KES) block. To achieve a high throughput rate, the inner signals, such as the syndrome, error locator and error value polynomials, are computed in parallel. In addition, the key equations are solved by using the S-DCME algorithm to reduce the hardware complexity. To handle the many problems caused by applying the S-DCME algorithm to the KES block, we modify the architectures of some of the blocks in the threeparallel RS decoder. The proposed RS architecture can reduce the hardware complexity by about 80% with respect to the KES block. In addition, the proposed RS architecture has an approximately 25% shorter latency than the conventional parallel RS architectures.

show abstract

Section: Resultsmentioning

confidence: 99%

Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications

Lee

Sunwoo

2010

J Sign Process Syst

View full text Add to dashboard Cite

show abstract

“…Reed-Solomon (RS) codes have been widely used in many kinds of modern communication systems, such as satellite communication system (DVB-S), star-earth link system (ShiJian-V), as well as optical communication system (10GBase-LR) [1,2]. RS (244,212) is recommended by CAST for the wideband multimedia satellite communication system.…”

Section: Introductionmentioning

confidence: 99%

“…KES block, which is considered as the most complex block, occupies more than 60%-80% area of the whole decoder [1]. Many implementations of KES have been proposed to downsize the VLSI area.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Area-efficient reed-solomon decoder for 10Gbps satellite communication

Zhang

Liu

Yang

2011

IEICE Electron. Express

View full text Add to dashboard Cite

The decoder is implemented and verified in FPGA, and can work at 178 MHz in Virtex2P. Thus a 8-channel FPGA implementation can be used for 10 Gbps satellite communication systems. Additionally, the decoder is also synthesized in Chartered 90 nm CMOS technology, and compared with previous decoders. The results show the decoder is more area-efficient than previous decoders. Meanwhile, by using this CMOS technology, the decoder can be clocked at about 1350 MHz, so a single-channel ASIC implementation can meet the requirement of 10 Gbps satellite communication.

show abstract

“…For example, a Super-FEC that uses a combination of two FEC codes is well known, such as [RS code+RS code], [BCH code+BCH code], and [RS code + BCH code]. Also, the development of very high-speed data transmission techniques for optical fiber communication systems have necessitated the implementation of high-speed FEC architectures to meet the continuing demand for ever-higher data rates [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications

Lee

Kang

Park

et al. 2010

J Sign Process Syst

Self Cite

View full text Add to dashboard Cite

This paper presents a two-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its highspeed low-complexity two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. A low-complexity syndrome computation architecture and a high-speed dual-processing pipelined simplified inversonless Berlekamp-Massey (DualpSiBM) key equation solver architecture were applied to the proposed concatenated BCH decoder with an aim of implementing a high-speed low-complexity decoder architecture. Two-parallel processing allows the decoder to achieve a high data processing rate required for 100 Gb/s optical communication systems. Also, the proposed two-iteration concatenated BCH code structure with block interleaving methods allows the decoder to achieve 8.91dB of net coding gain performance at 10 −15 decoder output bit error rate to compensate for serious transmission quality degradation. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s optical communications.

show abstract

Two-parallel Reed-Solomon based FEC architecture for optical communications

Cited by 24 publications

References 6 publications

Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications

Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications

Area-efficient reed-solomon decoder for 10Gbps satellite communication

A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications

Contact Info

Product

Resources

About