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This paper describes implementation of an applicationspecific DSP for OFDM modem systems. The proposed instructions can support computations of various blocks in OFDM systems. The Data ALU is specially designed and optimized for the proposed instructions. Performance comparisons show that the number of clock cycles improves over 10 % compared with Carmel DSP and over 50 % compared with TMS320C62X for FFT computation. However, the size of the DSP is much smaller than existing DSPs. The proposed architecture is implemented using iPROVE FPGA board and verification is performed using assembly programs that implement most of OFDM blocks. The SQNR value of FFT output is about 71 dB.

A simplified soft-decision demapping algorithm for digital video broadcasting via satellite, second generation (DVB-S2), is presented. The proposed algorithm can reduce the computational complexity required to compute the log likelihood ratio values between the received noisy symbol and possible constellation points compared to conventional algorithms. The simulation results show that the proposed algorithm has negligible performance degradation compared with conventional algorithms. Compared with the maximum algorithm, the proposed algorithm can reduce the hardware resources required by about 81%.Introduction: In conventional wireless communication systems, the log likelihood ratio (LLR) method has been used as a soft decision technique for the iterative coding scheme, soft input soft output (SISO) [1]. However, this method has problems in terms of its hardware complexity and power consumption, owing to the complicated operations involved. To overcome these problems, various soft decision techniques have been proposed [2,3]. The maximum (MAX) method can reduce the number of exponential and logarithm functions as compared to the LLR method. Hence, its hardware complexity is lower than that of the LLR method. The Euclidean method can reduce the number of multiplications of the channel estimation value. However, this method requires square and square root operations, thereby increasing the hardware complexity compared with the MAX method. In addition, the bit error rate (BER) performance is deteriorated compared to the LLR and MAX methods. In this Letter, we propose a simplified soft-decision demapping algorithm. The proposed algorithm can reduce the computation complexity compared with the conventional soft-decision method [1][2][3]. Compared with the MAX method, the proposed algorithm can reduce the hardware resources required by about 81%.

This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed architecture uses a single-memory for a small hardware size and uses a radix-4 algorithm for high speed. Its memory is partitioned into four banks for high-speed computation. It uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. The architecture has been modeled by VHDL and logic synthesis has been performed using the SamsungTM 0 . 5~ SOG cell library (KG80). The implemented FFT processor consists of 98,326 gates excluding RAM. The processor can operate at 42MHz and calculate a 256-point complex FFT in 6ps.