This paper proposes a high-speed and areaefficient three-parallel Reed-Solomon (RS) decoder using the simplified degree computationless modified Euclid (S-DCME) algorithm for the key equation solver (KES) block. To achieve a high throughput rate, the inner signals, such as the syndrome, error locator and error value polynomials, are computed in parallel. In addition, the key equations are solved by using the S-DCME algorithm to reduce the hardware complexity. To handle the many problems caused by applying the S-DCME algorithm to the KES block, we modify the architectures of some of the blocks in the threeparallel RS decoder. The proposed RS architecture can reduce the hardware complexity by about 80% with respect to the KES block. In addition, the proposed RS architecture has an approximately 25% shorter latency than the conventional parallel RS architectures.
This paper proposes a high-speed and area-efficient threeparallel RS decoder using the simplified degree computationless modified Euclid (S-DCME) algorithm for the key equation solver (KES) block. To achieve high throughput rate, three inner signals such as syndrome, error locator and error value polynomials are computed in parallel. In addition, the key equation is solved by using the S-DCME algorithm to reduce hardware complexity. To resolve the problem caused by using S-DCME to KES block of parallel architecture, we assign an inner reset signal to settle the problem. The proposed KES block can reduce about 80% of hardware complexity. In addition, the proposed RS architecture has approximately 25% shorter latency compared with conventional parallel RS architectures.
The original version of this article unfortunately contained a mistake on the acknowledgements. The one of the acknowledgement was misstated and should be corrected. A sentence about the IT R&D program of MKE/KEIT has to be revised to NRF and international cooperation program. A corrigendum is summarized as below.
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