High-speed architecture for three-parallel Reed-Solomon decoder using S-DCME

Abstract

This paper proposes a high-speed and area-efficient threeparallel RS decoder using the simplified degree computationless modified Euclid (S-DCME) algorithm for the key equation solver (KES) block. To achieve high throughput rate, three inner signals such as syndrome, error locator and error value polynomials are computed in parallel. In addition, the key equation is solved by using the S-DCME algorithm to reduce hardware complexity. To resolve the problem caused by using S-DCME to KES block of parallel architecture, we assign an inner reset signal to settle the problem. The proposed KES block can reduce about 80% of hardware complexity. In addition, the proposed RS architecture has approximately 25% shorter latency compared with conventional parallel RS architectures.