A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications

Lee, Kihoon; Kang, Han-Gil; Park, Jeong-In; Lee, Hanho

doi:10.1007/s11265-010-0519-0

Cited by 18 publications

(8 citation statements)

References 6 publications

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“…In this section, the performance of the proposed concatenation scheme that uses RS over GF (2 8 ) as an outer code and the SPC code (8,7,2) as an inner code is evaluated. Simulation of the concatenated scheme is carried out using BPSK modulation over an AWGN channel and Rayleigh fading channels.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Although the serial concatenation of RS and the convolutional code has gained so much interest and has been standardized in many communication systems, the serial concatenation of RS and an inner binary block code have been the focus of many researchers for different applications [5]. Different configurations including single and multi-level concatenations and various parallel schemes are investigated in [6] and [7]. Moreover, Justesen codes form a class of error detection and correction codes which are derived from RS codes and have good error-control properties [8].…”

Section: Introductionmentioning

confidence: 99%

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Efficient Low-Complexity Decoding of CCSDS Reed–Solomon Codes Based on Justesen’s Concatenation

et al. 2019

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Forward error correction (FEC) is a key capability in modern satellite communications that provide the system designer with the needed flexibility to comply with the different applications' requirements. Reed-Solomon (RS) codes are well known for their ability to optimize between the system power, bandwidth, data rate, and the quality of service. This paper introduces an efficient decoding scheme for decoding the RS codes adhering to the Consultative Committee for Space Data Systems (CCSDS) standards based on Justesen's construction of concatenation. To maintain the standard output size, the proposed scheme first encodes every m − 1 bits using the single-parity-check (SPC) code, while the RS code encodes K SPC codewords into N symbols that are of the same size as CCSDS standard. Decoding on the inner SPC code is based on maximum-likelihood decoding Kaneko algorithm, while for the proposed coding scheme, the reduced test-pattern Chase algorithm is adapted for decoding the outer RS code. The simulation results show the coding gains of 1.4 and 7 dB compared with the algebraic decoding of RS codes over the AWGN and Rayleigh fading channels, respectively. Moreover, the adopted reduced test-pattern Chase algorithm for decoding the RS code achieves an overall complexity reduction of 40% compared with the conventional Chase decoding algorithm. INDEX TERMS CCSDS, chase algorithm, concatenated codes, Justesen code, Reed-Solomon code, single-parity-check.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Efficient Low-Complexity Decoding of CCSDS Reed–Solomon Codes Based on Justesen’s Concatenation

et al. 2019

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“…Three-error-correcting BCH codes have very short decoding latency. They can be also utilized as the component codes of product or product-like codes to achieve very high decoding speed and good error-correcting performance [9]- [12].…”

Section: B Three-error-correcting Bch Decodermentioning

confidence: 99%

“…Decoders for product codes can achieve very high throughput since the component codes are short and the decoding of all codewords in the same dimension can be done in parallel. In particular, three-error-correcting BCH codes have been utilized as component codes to achieve throughput beyond hundreds of Gigabit/s for optical transport networks [9]- [12].…”

Section: Introductionmentioning

confidence: 99%

VLSI Architectures for Reed–Solomon Codes: Classic, Nested, Coupled, and Beyond

Zhang

2020

IEEE Open J. Circuits Syst.

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Classic Reed-Solomon (RS) codes and binary Bose-Chaudhuri-Hocquenghem (BCH) codes, which can be considered as a special case of RS codes, are utilized for error correction in numerous systems, such as Flash memories, optical communications, wireless communications, magnetic storage, and deep-space probing. Additionally, RS and BCH codes are interleaved/nested to form highgain coding schemes, including product and product-like codes and the recent generalized integrated interleaved codes, which are among the most promising candidates to address the hyper-speed and excellent-correction-capability requirements posed by next-generation terabit/s digital communications and storage. In recent developments, RS codes are also split/nested/coupled to form locally recoverable erasure codes and minimum storage regenerating codes that substantially improve the efficiency of failure recovery and enable the continued scaling of large-scale distributed storage. In this paper, prominent decoder architectures for classic RS/BCH codes are elaborated and the fundamental mathematical reformulations leading to the architectures are explained. Then the challenges and recent advancements on the decoder design of nested RS/BCH codes are highlighted. Erasure-correcting RS decoders for failure recovery are also briefly discussed. The goal of this paper is to provide comprehensive understanding of state-of-the-art VLSI architectures for classic RS/BCH codes and introduce the most recent architectures for new coding schemes built by nesting/coupling RS/BCH codes for emerging applications.

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“…RS(450,406) can corrects up to 22 symbol errors. Reed Solomon(RS) codes are based on Galois Field(GF) [4], [5], [6]Arithmetic. Forward error correction (FEC) is the error controlling method by adding redundant bits in the original message as shown in Fig.…”

mentioning

confidence: 99%

Forward Error Correction For Gigabit Automotive Ethernet using RS(450,406) Encoder

2019

IJITEE

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Error correction and detection during data transmission is a major issue. For resolving this, many error correction techniques are available. The Reed-Solomon coding is the most powerful forward error correction technique used in Gigabit Automotive Ethernet to compact channel noise during data transmission. The car becomes more smarter day by day and more new advanced electronics is being used in-vehicle. Gigabit Automotive Ethernet(1000BASE-T1) provide fast bandwidth for many kinds of applications and connect different functional parts in the car. The Reed Solomon(RS) coding is the powerful forward error correction(FEC) technique used in 1000BASE-T1 Automotive Ethernet. RS(450,406) coding is also known as shortened Reed Solomon codes. The Reed Solomon(RS) codes are generally used in communication system due to its ability of correcting both random and burst errors. Reed Solomon codes are no-binary systematic linear block codes. RS coding is widely used in high speed communication system. This RS code is implemented using Galois field(GF). The Automotive Ethernet is encoded using RS(450,406) codes through GF(512) for FEC. This RS codes can corrects the error up to t=22 symbol, while other encoding techniques corrects the error in t bits. In this paper we implemented the RS(Reed Solomon) code in Cadence ncsim Verilog software and used Cadence Simvision for showing timing diagrams. This RS code uses 9-bit based shortened (450,406) code.

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A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications

Cited by 18 publications

References 6 publications

Efficient Low-Complexity Decoding of CCSDS Reed–Solomon Codes Based on Justesen’s Concatenation

Efficient Low-Complexity Decoding of CCSDS Reed–Solomon Codes Based on Justesen’s Concatenation

VLSI Architectures for Reed–Solomon Codes: Classic, Nested, Coupled, and Beyond

Forward Error Correction For Gigabit Automotive Ethernet using RS(450,406) Encoder

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