Two novel ultra high speed carbon nanotube Full-Adder cells

Navi, Keivan; Momeni, Amir; Sharifi, Fazel; Keshavarzian, Peiman

doi:10.1587/elex.6.1395

Cited by 33 publications

(32 citation statements)

References 8 publications

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“…The¯rst category contains low-frequency full adders such as FA, 16 FA, 19 FA, 21 FA 22 and FA. 23 The second category contains high-frequency Full Adders such as FA, 17 FA, 15 FA, 18 FA, 20 FA, 40 and the proposed cell (Design3). Moreover, the best PDP belongs to CNT-Design3 at all frequencies.…”

Section: Operating Frequencymentioning

confidence: 99%

High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells

Mehrabani

Eshghi

2015

J CIRCUIT SYST COMP

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In this paper, three CNT-based full adder designs, called Design1, Design2 and Design3, are proposed. In these designs 12, 14 and 16 transistors are used, respectively. In all designs only 3-input NAND, Majority-not and NOR functions are used. First, a preliminary structure (De-sign1) is presented using 12 transistors. Then its weaknesses are tackled in two steps. In fact, in each step a new design is presented by adding two more transistors to its predecessor. Therefore two new structures called Design2 and Design3 are built in which Design3 is the most e±cient one. To study the performance of Design3 versus other silicon-based and CNT-based 32-nm classical and state-of-the-art cells, comprehensive simulations with regard to various supplies, loads, operating frequencies, and temperatures are performed using Synopsys HSPICE tool. Simulation results con¯rm that the proposed cell is superior to the other cells. At last the robustness of Design3 against the diameter mismatches of CNTs which is one of the most important concerns of nanoelectronics is studied using Monte Carlo transient analysis. This simulation reveals that Design3 functions very well against manufacturing process variations.

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Section: Operating Frequencymentioning

confidence: 99%

High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells

Mehrabani

Eshghi

2015

J CIRCUIT SYST COMP

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“…There are only five CNTFET-based adders in the literature, all of which have been compared with our design. Design 1 [21], design 1 in [22], which is the same as design 2 in [21], the proposed adder in [22], and the presented full adder in [19] are called CNTD1, CNTD2, CNTD3, and CNTD4 in this paper.…”

Section: Simulation Environmentmentioning

confidence: 99%

“…In this paper, CNFET technology has been employed, to make a very high-performance and ultra-low-power adder from the proposed design. Only three CNTFET-based full adder cells have been presented so far [19,[21][22][23]. However, parasitic capacitances and layout effects have not been considered in them.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of a New Carbon Nanotube Full Adder Cell

Ghadiry

Manaf

Ahmadi

et al. 2011

Journal of Nanomaterials

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A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.

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“…This design is based on the idea that the C out function is the same as 3-input majority function shown in (3) [4]. …”

Section: Proposed Full Adder Cellmentioning

confidence: 99%

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mentioning

confidence: 99%

A Low-Voltage and Energy-Efficient Full Adder Cell Based on Carbon Nanotube Technology

et al. 2010

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[4,5], arithmetic circuits [6] and so on, taking advantages of its unique attributes. However, among these circuits arithmetic circuits could be more interesting, due to their vast range of applications. Many VLSI systems such as microprocessors, DSP architectures and nano-micro systems [7,8,9] have arithmetic unit, which is also included in their critical path. One of the most important and basic arithmetic units is Full Adder, which could be the basic structure of many complex arithmetic systems and as a results its performance directly affects the performance of the whole system. Therefore, it is necessary to design novel Full Adder structures with higher performance and lower power consumption, based on the emerging nano technologies. In this paper a new energy-efficient 1-bit Full Adder cell is proposed, which takes advantage of CNFET devices and high density Carbon Nanotube Capacitors (CNCAP) [10]. The proposed circuit is also compared with the classical and state-of-the-art CMOS and CNFET-based Full Adders, with different styles, which are briefly introduced in this section.

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Two novel ultra high speed carbon nanotube Full-Adder cells

Cited by 33 publications

References 8 publications

High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells

High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells

Design and Analysis of a New Carbon Nanotube Full Adder Cell

A Low-Voltage and Energy-Efficient Full Adder Cell Based on Carbon Nanotube Technology

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