Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT (Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET (Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP (Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages. Citation: Keivan Navi, Rabe'e Sharifi Rad, Mohammad Hossein Moaiyeri and Amir Momeni, "A low-voltage and energy-efficient full adder cell based on carbon nanotube technology", Nano-Micro Lett. 2, 114-120 (2010). doi:10.5101/ nml.v2i2.p114-120 Scaling down the feature size of MOSFET devices in nanometer, leads to serious challenges, such as short channel effects, very high leakage power consumption and large parametric variations. Due to these limitations researchers become eager to work toward new emerging technologies such as Quantum Automata (QCA) [1], Nanowire transistors [2] and Carbon Nanotube Field Effect Transistors (CNFET) [3]. By the mentioned problems of nanoscale CMOS technology, which makes it unsuitable for low-power and low-voltage applications in the near future, these nano-devices could replace the conventional silicon MOSFET in the time to come. However, due to the similarities between the infrastructure and functionality of the conventional MOSFET devices with CNFETs and also because of the ballistic operation of CNFETs, it could be more promising and achievable, compared to other nano-devices. Recently some efforts have been done for designing circuits based on CNFET such as multiple valued logic circuits [4,5], arithmetic circuits [6] and so on, takingadvantages of its unique attributes. However, among these circuits arithmetic circuits could be more interesting, due to their vast range of applications. Many VLSI systems such as microprocessors, DSP architectures and nano-micro systems [7,8,9] have arithmetic unit, which is also included in their critical path. One of the most important and basic arithmetic units is Full Adder, which could be the basic structure of many complex arithmetic systems and as a results its performance directly affects the performance of the whole system. Therefore, it is necessary to design novel Full Adder structures with higher performance and lower power consumption, based on the emerging nano technologies. In this paper a new energy-efficient 1-bit Full Adder cell is proposed, which takes advantage of CNFET devices and high density Carbon Nanotube Capacitors (CNCAP) [10]. The proposed circuit is also compared with the classical and state-of-the-art CMOS and CNFET-based Full Add...
[4,5], arithmetic circuits [6] and so on, taking advantages of its unique attributes. However, among these circuits arithmetic circuits could be more interesting, due to their vast range of applications. Many VLSI systems such as microprocessors, DSP architectures and nano-micro systems [7,8,9] have arithmetic unit, which is also included in their critical path. One of the most important and basic arithmetic units is Full Adder, which could be the basic structure of many complex arithmetic systems and as a results its performance directly affects the performance of the whole system. Therefore, it is necessary to design novel Full Adder structures with higher performance and lower power consumption, based on the emerging nano technologies. In this paper a new energy-efficient 1-bit Full Adder cell is proposed, which takes advantage of CNFET devices and high density Carbon Nanotube Capacitors (CNCAP) [10]. The proposed circuit is also compared with the classical and state-of-the-art CMOS and CNFET-based Full Adders, with different styles, which are briefly introduced in this section.
In this study, we present a very quick full adder cell that has high energy efficiency based on carbon nano-tube transistor technology This project and other circuits in this study were in different voltages and frequencies with HSPICE software .The results of show that the speed and efficiency of this circuit is obviously better than other circuits like: CMOS and CNFET. Also, this full adder that we present, make great ability to on outlet and it works properly in low voltages.
Ada has an important role in the real-time/embedded/safety-critical areas. It is the only ISO-standard, object-oriented, concurrent, real-time programming language. Ada is used as a usual language for application areas such as defense embedded systems that reliability and efficiency are very essential. One of the main Ada's characteristics in compare with other programming languages is that, Ada was developed from the ground up with capabilities that provide real-time requirements. In this study it will be shown why Ada is used as the new standard for real-time programming languages and basic characteristics of real-time programming system in general and how they are addressed in Ada will be explained.
Reliable and real-time packet transmissions along with minimum energy consumption are main challenges in designing routing protocols to realize many applications of Wireless Sensor Networks (WSNs). With considering these challenges, we proposed a novel Geographical Reliable and Real-time routing Protocol (GRRP) which takes energy consumption into account. This protocol is based on two new approaches called geographical area divisions and efficient node selection function. GRRP makes use of these approaches to determine the best geographical angle and optimum nodes in the angle. In order to hit its goals, GRRP utilizes a novel multi-path routing algorithm. As the simulation results indicate, GRRP outperforms state-of-the-art protocols in terms of average end-to-end delay, throughput and reliability.
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