Design and Analysis of a New Carbon Nanotube Full Adder Cell

Carbon nanotube field-effect transistors (CNFETs) utilize an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure, which holds great promise for the future of integrated circuits. In this paper, a full adder cell based on a parallel design using CNFETs is presented. The main objective of designing this full adder cell is to reduce critical path delay in CNFET-based adder circuits. The proposed design positively affects speed and power consumption by shortening the data path. In order to evaluate the proposed design, several simulations were performed with different load capacitors, frequencies, and temperatures using HSPICE in 32-nm CMOS and 32-nm CNFET technologies. The proposed full adder cells were compared with five other full adder cells using 4-bit ripple carry adder (RCA) and 8-bit RCA circuits with power consumption, speed, and power delay product parameters. The obtained results indicate that the proposed design is faster than other designs due to a shortened data path. The results of the simulations confirm the higher efficiency of the proposed full adder cell with respect to other designs.

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“…The other design is CNFETFA-2, which was presented in [11]. The circuit of this full adder cell is shown in Figure 5.…”

Section: Previous Workmentioning

confidence: 99%

A CNFET full adder cell design for high-speed arithmetic units

Ghanatghestani¹,

Ghavami²,

Salehpour³

2017

Turk J Elec Eng & Comp Sci

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“…The emerging new generation of transistors such as CNTFET (Carbon Nano Tube Field Effect Transistor), has helped in overcoming some limitations of CMOS technology. Therefore, many of these full adders are designed using this new technology [8][9][10][11][12][13]. CNTFET transistors have better performance compared to CMOS transistors.…”

Section:  mentioning

confidence: 99%

“…Also, another kind of full adder based on intermediate XOR or XNOR logic and transmission gate is the CNTFA which is designed based on CNTFET technolgy [20]. This CNTFA full adder is shown in Figure 5.…”

Section: Previous Workmentioning

confidence: 99%

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CNTFET-Based Design of a High-Efficient Full Adder Using XOR Logic

Hatefinasab¹

2016

J. Nano- Electron. Phys.

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This paper presents a new low power and high speed full adder based on Carbon Nano Tube Field Effect Transistor (CNTFET) technology. This proposed full adder is based on a XOR logic function using 32 nm CNTFET technology. The MOSFET-like CNTFET is applied in this paper to use CMOS (Complementary Metal Oxide Semiconductor) logic gate. The better structure of CNTFET transistors can improve the performance of full adder based on CNTFET technology [1]. The proposed full adder is simulated in different frequencies, various supply voltages, temperatures and load capacitances to prove better performance in different conditions using the Synopsys HSPICE simulator software in comparison with previous full adders in CNTFET technology.

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“…Recent experimental studies have discussed the feasibility of manufacturing graphene nanoribbon transistors [5,6]. The majority of scientists have become interested in this area and presented various types of GNR transistor features and applications [7][8][9][10][11][12][13][14]. However, there is an absence of research in modelling those features close to the drain junction, which is known breakdown voltage.…”

Section: Introductionmentioning

confidence: 99%

Effect of Device Variables on Surface Potential and Threshold Voltage in DG-GNRFET

Mehrdel

Aziz

Ghadiri

2015

IJECE

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<p><em>In this paper we present four simple analytical threshold voltage model for short- channel and length of saturation velocity region (LVSR) effect that takes into account the built – in potential of the source and drain channel junction, the surface potential and the surface electric field effect on double – gate graphene nanoribbon transistors. Four established models for surface potential, lateral electric field, LVSR and threshold voltage are presented. These models are based on the easy analytical solution of the two dimensional potential distribution in the graphene and Poisson equation which can be used to obtain surface potential, lateral electric field, LVSR and threshold voltage. These models give a closed form solution of the surface potential and electrical field distribution as a function of structural parameters and drain bias. Most of analytical outcomes are shown to correlate with outcomes acquired by Matlab simulation and the end model applicability to the published silicon base devices is demonstrated.</em></p>

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Design and Analysis of a New Carbon Nanotube Full Adder Cell

Cited by 16 publications

References 23 publications

A CNFET full adder cell design for high-speed arithmetic units

A CNFET full adder cell design for high-speed arithmetic units

CNTFET-Based Design of a High-Efficient Full Adder Using XOR Logic

Effect of Device Variables on Surface Potential and Threshold Voltage in DG-GNRFET

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