Tunneling oxide engineering for improving retention in nonvolatile charge-trapping memory with TaN/Al₂O₃/HfO₂/SiO₂/Al₂O₃/SiO₂/Si structure

Abstract

In this paper, we demonstrate retention improvement in nonvolatile charge-trapping memory cells by tunneling oxide engineering with Al 2 O 3 . By utilizing SiO 2 /Al 2 O 3 /SiO 2 layers for the tunneling oxide, it is shown that the threshold voltage window after 10 years is significantly improved from 0.78 V to 4.18 V through Synopsys Sentaurus technology computer-aided design simulation. In addition, retention improvement from incorporating SiO 2 /Al 2 O 3 /SiO 2 tunneling layers is compared with that using SiO 2 /Si 3 N 4 /SiO 2 tunneling layers. The relationship between charge-trapping layer thickness and trapped charge emission is also investigated. As a result, we open up the possibility of using HfO 2 as a charge-trapping layer with significant reliability enhancement.

Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

“…In previous research, the advanced bandgap-engineered TaN/Al 2 O 3 /HfO 2 /SiO 2 /Si (BE-TAHOS) structure has been investigated for a faster erasing speed and larger memory window by incorporating Si 3 N 4 at the tunneling oxide layer [37][38][39][40][41][42][43][44]. By utilizing this BE-TAHOS structure [34][35][36] and applying Al 2 O 3 at the tunneling layer, the advanced structure of TaN/Al 2 O 3 /HfO 2 /SiO 2 /Al 2 O 3 /SiO 2 /Si (TAHOAOS) is designed for NOR flash memory.…”

“…Since the EOT of the three structures is the same, the initial transfer characteristics are almost the same, as shown in Figure 3. Second, the bottom gate was added to suppress programming of the unselected cell and solve disturbance issues [37]. Specifically, as illustrated in Figure 4, the additional bottom gates are connected with each other by the bottom gate line, which is perpendicular to the source line and word line.…”

“…From this perpendicular design between the bottom gate line and word line, it is possible to program the selected cell only and inhibit programming of unselected cells, as described in the following paragraph. Second, the bottom gate was added to suppress programming of the unselected cell and solve disturbance issues [37]. Specifically, as illustrated in Figure 4, the additional bottom gates are connected with each other by the bottom gate line, which is perpendicular to the source line and word line.…”

“…This is because the conventional HCI programming consumes significant power due to a significant drain current during programming [48]. On the other hand, FN programming can lower power consumption [37] due to its lower gate current compared to the higher drain current during HCI programming [48]. Therefore, FN tunneling is adopted for programming with low power consumption.…”

“…Consequently, it has been demonstrated that the retention characteristics can be significantly improved in a high-κ-based NOR flash memory device by utilizing the advanced tunneling layers with SiO 2 /Al 2 O 3 /SiO 2 on the tunnel field effect transistor (TFET) structure, which has been broadly studied for low power application [37][38][39][40][41][42][43][44]. From an array perspective, it has been demonstrated that the proposed memory device structure is also able to inhibit the programming in unselected cells by bottom gate effect.…”