In this paper we p resent an empirical preliminary model able to simulate the degradation with t ime in the gate leakage current in GaN HEMT devices. The model is based on extensive reverse and forward current measurements, carried out on a wide range of different device designs and under different bias, performed over aged transistors by III-V Lab (Alcatel-Thales) within the European KORRIGA N. A closed form expression for the reverse gate current, depending on time, as well as the expression parameters extraction procedure are presented. The experimental and simulated results presented illustrate the validity of the model as well as it's usefulness in reliability studies.