Tuning Hyrbrid Ferroelectric and Antiferroelectric Stacks for Low Power FeFET and FeRAM Applications by Using Laminated HSO and HZO films

Abstract

The properties of hybrid ferroelectric (FE) and antiFE (AFE) films integrated in a single capacitor stack is reported. The stack lamination (4 × 5 nm) or (2 × 10 nm) using an Alumina (Al2O3) interlayer, material type (Si‐doped HfO2 (HSO) and Zr doped HfO2 (HZO)), precursor condition (TEMA‐Hf and Hf/ZrCl4), or dopant concentration (Si and Zr) are investigated for laminate stack properties. Optimized FE properties (higher 2Pr and a lower fraction of the monoclinic phase) are observed at (2 × 10 nm) laminates compared to a single 20 nm film thickness. The hybrid laminate stack as FE‐FE, AFE‐FE, DE‐FE, or DE‐AFE using (2 × 10 nm) based laminates are explored in terms of the output FE hysteresis (2Pr, 2Ec) and structural properties by X‐ray diffraction. The hybrid AFE‐FE stack shows the potential of tailoring the output FE hysteresis 2Ec by varying the fraction of the AFE phase. The hybrid AFE‐FE stack is studied for the HSO and HZO materials at optimal FE content for the first laminate layer while varying the Si or Zr content to stabilize different degrees of an AFE phase in the second laminate layer. The superposition of the hybrid AFE‐FE hysteresis shows a systematic 2Ec control. A model is developed to describe the tailored output FE hysteresis via the tuning of a hybrid AFE‐FE stack. The role of stack lamination at hybrid‐stabilized phases inside a single stack is explored with the aim for a controlled and optimized FE hysteresis shape toward a low power (2Ec) operation.

Effect of Al2O3 interlayers on the microstructure and electrical response of ferroelectric doped HfO2 thin films

“…Since increasing antiferroelectric-like behavior is observable with thinner layers and the TKD measurements revealed an [001] inplane texture, it fits very well with previously published results which provided evidence that the antiferroelectric-like behavior is related to 90 °-domain wall movement Lederer et al (2021e). As 90 °domain wall movement is affected by mechanical stress due to its ferroelastic behavior, increased tensile in-plane stress due to the thinner layer will consequently lead to increased antiferroelectric-like behavior Lederer et al (2021e); Ali et al (2022); Lederer et al (2021c); Kirbach et al (2021). An important finding here is that these effects are also present in HZO layers, as indicated by the shift in the optimum doping concentration, thus providing evidence that these mechanisms are applicable for the HfO 2 /ZrO 2 material system in general.…”

Fluorite‐Structured Ferroelectric and Antiferroelectric Materials: A Gateway of Miniaturized Electronic Devices

“…Thus, hybrid stacks of FE and AFE layers can enable a superposition of ferroelectric hysteresis that exhibit a lower coercive field. [105] The degree of AFE change in one layer can affect the magnitude of coercive field reduction of the output FE hysteresis (Figure 25). The electric and stress-coupled effects between the two layers produce FE hysteresis with modulated effect on the coercive Reproduced with permission.…”

“…The P-E hysteresis of the laminate (2 × 10 nm) HSO and HZO using Hf/ZrCl4 based precursor illustrated for a) the FE-FE based stack, b-d)the hybrid AFE-FE stack at varying degree of the AFE phase. Reproduced with permission [105]. Copyright 2022, Wiley.…”

“…The comparison between the electrostatic behavior of ZrO 2 AFE based planar and 3D structures: a) polarization hysteresis loops of 3D and planar capacitors, b) ESD and η of the 3D (inset) and planar capacitors, showing electric field cycling stability,and c) SEM top image and TEM cross-sectional images of 3D capacitors. Reproduced with permission [105]. Copyright 2016, Wiley.…”

Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

“…Mitigation Strategies. Processing/technology strategies to improve endurance and reduce degradation of the gate stack involve: i) operation in minor loops instead of the fully saturated P-V loop [103], ii) employment of high-𝜅 oxides as IL or as seed layer [20], [77], [83], [104], [105], iii) resorting to MFMIS structures (i.e., HfO2-FeCAP in the back-end and MOSFET in the front-end) and engineering the ferroelectric/transistor area ratio [33], [34], iv) reducing the charge mismatch between the ferroelectric polarization and the semiconductor charge by engineering Pr and/or εFE [12], [20], v) improving the quality of IL layer by high-pressure hydrogen annealing (HPHA) [106] or possibly by NH3 plasma treatment combined with MWA [70], and vi) reducing oxygen vacancies formation by employing ruthenium (or other metals) as the gate electrode [107] vii) material-optimization strategies (e.g., nanolaminates, AFE/FE stacks) [108], [109]. On top of these strategies, it is possible to improve endurance by electrical techniques [20] that involve proper de-trapping sequence and delays [74], [79] or performing fast I-V reads [77] during cycling to reduce VTH shifts due to traps, or to apply self-heating pulses in between writing cycles to partially redistribute the generated defects from the IL to the FE-HfO2 [87].…”