Tunable Mobility in Double-Gated MoTe₂ Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites

Abstract

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Controllable P‐ and N‐Type Conversion of MoTe2 via Oxide Interfacial Layer for Logic Circuits

“…Furthermore, the growth of Al 2 O 3 on a 2D‐TMDC is beneficial in terms of precise thickness control, low‐temperature growth, and good sticking to most of the 2D‐TMDC material's surface compared with other oxide materials. In addition, when Al 2 O 3 is used as a dielectric in TMDC‐based transistors, it can improve the mobility of the channel by reducing the Coulombic scattering . It is worth to mention here that for the encapsulation of p‐FETs, the oxide‐based dielectrics are not very favorable candidates which can bring oxygen atoms at the MoTe 2 surface and consequently can contribute in altering the FET performance.…”

Li Intercalation Effects on Interface Resistances of High‐Speed and Low‐Power WSe2 Field‐Effect Transistors

“…We modeled the R DS as a resistance formed by the contact resistance (R contact ) on the gold electrode (Au)/top surface of the WSe 2 interface and additional interlayer resistances (R int ) at each multilayers WSe 2 interlayer interface (Figure 2e). We extracted the R DS and R channel using the Y-function method (Note S1 and Figure S3, Supporting Information) [35][36][37][38][39] (Figure 2f). The total resistance (R total ) is the sum of R DS and R channel .…”

“…[41] For µ, we used low field-effect mobility (µ 0 ) for minimizing effect of filed effect and contact resistance. [35][36][37] This µ 0 of pristine and after-Li intercalation were extracted from the slope of the fitted linear line in Figure S3a, Supporting Information, [35][36][37][38][39] and were 2 cm 2 V −1 s −1 and 108 cm 2 V −1 s −1 , respectively. After Li intercalation, the 2D sheet doping concentration increased from 4.64 × 10 12 cm −2 to 4.9 × 10 12 cm −2 , which indicates enhancement of carrier concentration by about 2.6 × 10 11 cm −2 due to electron transfer from intercalated Li ions.…”

Bilayer Tellurene: A Potential p‐Type Channel Material for Sub‐10 nm Transistors

“…However, there are many efforts have been made for reducing the charge traps, such as replacing dielectric material (such as hexagonal boron nitride and Al 2 O 3 /HfO 2 ) and controlling DG bias independently, etc. [53][54][55] Hence, it is possible to achieve the trap-free atomically thin transistors in the future.…”