Tunable Charge-Trap Memory Based on Few-Layer MoS₂

Abstract

Charge-trap memory with high-κ dielectric materials is considered to be a promising candidate for next-generation memory devices. Ultrathin layered twodimensional (2D) materials like graphene and MoS2 have been receiving much attention because of their novel physical properties and potential applications in electronic devices. Here, we report on a dual-gate charge-trap memory device composed of a few-layer MoS2 channel and a three-dimensional (3D) Al2O3/HfO2/Al2O3 charge-trap gate stack. Owing to the extraordinary trapping ability of both electrons and holes in HfO2, the MoS2 memory device exhibits an unprecedented memory window exceeding 20 V. More importantly, with a back gate the window size can be effectively tuned from 15.6 to 21 V; the program/erase current ratio can reach up to 10 4 , far beyond Si-based flash memory, which allows for multi-bit information storage. Furthermore, the device shows a high mobility of 170 cm 2 V -1 s -1 , a good endurance of hundreds of cycles and a stable retention of ~28% charge loss after 10 years which is drastically lower than ever reported MoS2 flash memory. The combination of 2D materials with traditional high-κ charge-trap gate stacks opens up an exciting field of novel nonvolatile memory devices. KEYWORDS. Charge-trap memory, MoS 2 , Memory window, Dual gate, Memory characteristics 3 Atomically thin 2D materials like graphene and MoS 2 has been extensivelystudied recently because of their promising applications in optoelectronics 1, 2 , spintronics 3-7 , transparent and flexible devices [8][9][10][11][12] . Due to its remarkable properties, such as high carrier mobility and mechanical flexibility, graphene has been incorporated into nonvolatile memory structures serving as a floating gate 13,14 or a transparent channel 15 . However, owing to its zero band gap 16 , the graphene channeled memory devices typically possess a low program/erase current ratio, which significantly hinders its application in nonvolatile memory devices. Unlike graphene, MoS 2 has a transition from indirect band gap (1.2 eV) to a direct band gap (1.8 eV) in monolayer 17,18 . Its field effect transistors 19 show a high mobility of 200 cm 2 V -1 s -1 with a high on/off ratio approximately 10 8 . To potentially enhance the program/erase current ratio, attempts were made to replace graphene with MoS 2 as a channel material in a ferroelectric memory 20 or as a charge-trap layer in a graphene flash memory 21 . It was demonstrated that the monolayer MoS 2 is very sensitive to the presence of charges 14 . However, the relatively small memory window, the degraded mobility, and the insufficient trap capability in those devices require further improvement of the chargetrap stack in the MoS 2 memory device.

Nonvolatile Charge Injection Memory Based on Black Phosphorous 2D Nanosheets for Charge Trapping and Active Channel Layers

“…Figure 3b shows the variation in V TH as a function of the V G pulse width, which was directly determined from Figure 3a. The black line displays the initial V TH (1 V) value, and the blue (circle) and red (square) lines show the V TH shifts for electron (+20 V) and hole (−20 V) injection properties, respectively, when the V G pulse width changes from 100 μs to 3 s. The charge trapping rate (dN trap /dt) could be calculated from the V TH shifts using the following equations [43,44] …”

“…However, considering both the charge trap density and trapping rate, the BCIM 01 device exhibits a memory performance that is comparable to that of the state-of-the-art MoS 2 based CIM devices previously reported in the literature. [43,44] Additional details on the comparison with other 2D-based memory devices are summarized in Table S1 in the Supporting Information. Figure 3c shows the retention properties of the BCIM 01 device measured under a V D of −0.1 V and floating V G conditions following the +20 V (Program) and −20 V (Erase) V G pulses for 100 μs.…”

Phototunable Biomemory Based on Light‐Mediated Charge Trap

“…Conceivable‐resistive switching mechanisms in RRAM system consist of the formation of metal filament, the charge trapping/detrapping process, redox reaction of the insulating layer, or a combined mechanism 51, 52, 53, 54. First, we investigated the temperature dependence of the ON and OFF current of Al/CDs‐silk/ITO device (see Figure S8 in the Supporting Information).…”

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

“…18 Based on this equation, the density of the stored holes and electrons is estimated to be on the order of 10 13 cm −2 , indicating that the HfO 2 charge trapping layer exhibits strong potential for data storage.…”

“…However, the trade-off between data retention and program/erase speed is the main bottleneck for SONOS devices in replacing floating-gate ones. 12 Recently, high-κ dielectrics have been [13][14][15][16][17][18] Therefore, in this work, to further improve NOR-type flash memory performance, we propose and investigate a type of p-channel charge trapping FOI-MAHAS memory. In the Fabrication process section, we briefly introduce the specific process flow of the p-channel charge trapping FOI-MAHAS memory.…”