2004 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (IEEE Cat. No.04CH37530)
DOI: 10.1109/asmc.2004.1309536
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Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic

Abstract: A method for formation and control of silicon gates orfins uses trim of a hard mark by a new gaseous oxide etch.Logic blocks with two separately controlled gate lengths and dielectric thicknesses are embedded on chip.

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Cited by 4 publications
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“…The dHM process is also attractive as a less costly method than UV trimming 3 or chemical oxide removal. 2 With this process an ontrack wet trimming capability has been presented. The soluble hardmask has also enabled the imaging layer thickness to be less than one quarter of the exposure wavelength.…”
Section: Discussionmentioning
confidence: 99%
“…The dHM process is also attractive as a less costly method than UV trimming 3 or chemical oxide removal. 2 With this process an ontrack wet trimming capability has been presented. The soluble hardmask has also enabled the imaging layer thickness to be less than one quarter of the exposure wavelength.…”
Section: Discussionmentioning
confidence: 99%
“…[18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33] These chemistries were commercialized in the semiconductor industry for use in precleaning technologies in film deposition, silicidation, and the fabrication of high-k dielectric metal gates. [29][30][31][32][33] Very recently, the thermal cyclic etching of SiN has also been realized. [34][35][36] In principle, a thin surface modified layer comprising (NH 4 ) 2 SiF 6 forms on the surface in a self-limiting manner to protect a material from etching by preventing for the further exposure to etchants and can be removed by thermal annealing.…”
Section: Advances In Atomic Layer Processing For Emerging Materialsmentioning
confidence: 99%