Fabrication of Metal Gated FinFETs Through Complete Gate Silicidation With Ni

Kedzierski, J.; Ieong, M.; Kanarsky, T.; Zhang, Ying; Wong, H.-S. Philip

doi:10.1109/ted.2004.838448

Cited by 57 publications

(28 citation statements)

References 18 publications

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“…F IN-SHAPED field-effect transistors (FinFETs) are being considered as preferred devices for the sub-22-nm-node CMOS technologies [1], [2]. Multigate FinFET devices have shown excellent scalability and improved logic performance, as well as improved analog and mixed-signal circuit performance in sub-32-nm-node CMOS technologies [3]- [5] compared with planar bulk CMOS transistors.…”

Section: Introductionmentioning

confidence: 99%

A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

Shrivastava

Baghini

Sharma

et al. 2010

IEEE Trans. Electron Devices

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Abstract-For the first time, we propose a novel bottom spacer fin-shaped field-effect-transistor (FinFET) structure for logic applications suitable for system-on-chip (SoC) requirements. The proposed device achieved improved short-channel, powerdelay, and self-heating performance compared with standard silicon-on-insulator FinFETs. Process aspects of the proposed device are also discussed in this paper. Physical insight into the improvement toward the short-channel performance and power dissipation is given through a detailed 3-D device/mixed-mode simulation. The self-heating behavior of the proposed device is compared with standard FinFETs by using detailed electrothermal simulations. The proposed device requires an extra process step but enables smaller electrical width for self-loaded circuits and is an excellent option for SoC applications.Index Terms-Bulk fin-shaped field-effect transistor (FinFET), electrothermal, fin-shaped field-effect transistor (FinFET), selfheating, short-channel performance, spacer, width quantization.

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Section: Introductionmentioning

confidence: 99%

A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

Shrivastava

Baghini

Sharma

et al. 2010

IEEE Trans. Electron Devices

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“…1 To further miniaturize the transistor while still maintaining control over power consumption, alternative transistor geometries need to be considered. 1 Silicon nanowire based devices 2,3 and horizontal double-gate transistors, such as the Fin FET (FINFET), [4][5][6][7] have exhibited high device mobilities and significantly reduced SCEs on the sub-100-nm scale. The FINFETsa structure based on a silicon fin sandwiched between two gate electrodesshas clearly demonstrated that increasing the electrostatic efficiency of the gate electrode geometry is essential in reducing power consumption at this size scale.…”

mentioning

confidence: 99%

Silicon Vertically Integrated Nanowire Field Effect Transistors

et al. 2006

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Silicon nanowires have received considerable attention as transistor components because they represent a facile route toward sub-100-nm single-crystalline Si features. Herein we demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowire assembly processes. The device fabrication allows Si nanowire channel diameters to be readily reduced to the 5-nm regime. These first-generation vertically integrated nanowire field effect transistors (VINFETs) exhibit electronic properties that are comparable to other horizontal nanowire field effect transistors (FETs) and may, with further optimization, compete with advanced solid-state nanoelectronic devices.

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“…Double gate MOSFETs (DG) body potential, controlled from two sides due to this DG MOSFET, has higher short channel effect immunity [10]. FinFET a double gate device in which second gate is added opposite to the first gate has long been discerned for it has better control on short channel effect [11].…”

Section: Introductionmentioning

confidence: 99%

Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology

Yadav¹,

Khandelwal²,

Akashe³

2013

IJCA

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As technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks for many arithmetic circuits. This paper contrasts and evaluates the performance of conventional CMOS and FinFET based XOR-XNOR circuit design. It is based on the study of high speed, low power, and small area in XOR-XNOR digital circuits. The proposed FinFET based XOR and XNOR circuits have been designed using Cadence VIRTUOSO Tool applying voltage supply of 0.2 to 1.2 voltages, with temperature at 27 0 C and all the simulation results have been generated by Cadence SPECTRE simulator at 45nm technology. Simulation results exhibit low power, delay, power, delay product (PDP), and average dynamic power consumption.

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Fabrication of Metal Gated FinFETs Through Complete Gate Silicidation With Ni

Cited by 57 publications

References 18 publications

A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

A Novel Bottom Spacer FinFET Structure for Improved Short-Channel, Power-Delay, and Thermal Performance

Silicon Vertically Integrated Nanowire Field Effect Transistors

Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology

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