Trapping mechanisms in negative bias temperature stressed p-MOSFETs

Schlunder, C.; Brederlow, R.; Wieczorek, P.; Dahl, C.; Holz, Jürgen; Röhner, M.; Kessel, S.; Herold, Volker; Goser, K.; Weber, W.; Thewes, R.

doi:10.1016/s0026-2714(99)00107-9

Cited by 27 publications

(7 citation statements)

References 5 publications

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“…V T , I D , and l eff are determined from I D -V D and I D -V G measurements. The interface trap density D it is usually measured with charge pumping [45] or log(I D )-V G subthreshold swing measurements. Usually source, drain and substrate are grounded during the stress period.…”

Section: Measurementsmentioning

confidence: 99%

Negative bias temperature instability: What do we understand?

Schroder

2007

Microelectronics Reliability

334

134

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Section: Measurementsmentioning

confidence: 99%

Negative bias temperature instability: What do we understand?

Schroder

2007

Microelectronics Reliability

334

134

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“…NBTI for pMOSFETs describes the parameter degradation under a static stress mode at elevated temperature (Jeppson and Svensson, 1977;Schlünder et al, 1999;Krishnan et al, 2003;LaRosa et al, 1997). A high gate-source voltage drives the device in inversion.…”

Section: Negative Bias Temperature Instabilitymentioning

confidence: 99%

Device reliability challenges for modern semiconductor circuit design – a review

Schlunder

2009

Adv. Radio Sci.

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Abstract. Product development based on highly integrated semiconductor circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1). Degradation mechanisms like Negative Bias Temperature Instability (NBTI) or Hot Carrier Injection (HCI) lead to parameter drifts during operation adding on top of the process variations. The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs. An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR) will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.

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“…NBTI is nowadays the most critical device degradation mechanism and became a limiting factor in scaling of modern CMOS technologies [1][2][3][4][5][6]. Although the shrink of gate oxide thickness is almost stopped at current technologies under development, the NBTI challenge will increase furthermore.…”

Section: Introductionmentioning

confidence: 99%

Consideration of recovery effects during NBTI measurements for accurate lifetime predictions of state-of-the-art pMOSFETs

Heinrigs

Reisinger

Gustin

et al. 2007

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual

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The NBTI recovery phenomenon leads to a fast reduction of the stress induced electrical device parameter degradation after end of stress. Delay times between device-stress and -characterization within NBTI-experiments affect the measurement values of degradation. This work discusses the impact of these delays on lifetime prediction for technology qualifications. For this reason we investigate delay times from 1µs up to 60s and stress times from 100ms up to 250 000s. A correlation between stress time, delay time induced recovery and error in predicted lifetime is elaborated for the first time. The influence of the recovery on single device stress experiments, on the voltage acceleration and finally on lifetime extrapolation is discussed. Furthermore we give simple guidelines for measurement requirements and essential stress times for accurate lifetime evaluations.

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Trapping mechanisms in negative bias temperature stressed p-MOSFETs

Cited by 27 publications

References 5 publications

Negative bias temperature instability: What do we understand?

Negative bias temperature instability: What do we understand?

Device reliability challenges for modern semiconductor circuit design – a review

Consideration of recovery effects during NBTI measurements for accurate lifetime predictions of state-of-the-art pMOSFETs

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