Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks

Highly-stable black phosphorus field-effect transistors with low density of oxide traps

“…(1)-(4) allow us to obtain the D ot (V g ) distributions within the whole device operation range from −20 to 20 V. However, since we are here interested in the energy distributions of D ot , we next convert V g into the electronic energy E. In order to do this, we consider the band diagrams and the alignment of the defect bands in SiO 2 obtained using technology computer-aided design (TCAD) simulations. 30,31 From conventional Si technologies 24,32 and our previous work on BP devices 30 it is known that SiO 2 contains two distinct defect bands, whereby the upper defect band is most likely of acceptor-type (i.e., in equilibrium the defects are negatively charged below and neutral above the Fermi level) and the lower defect band is of donor-type (i.e., the defects are neutral below and positively charged above the Fermi level). The performance of BPFETs is mainly affected by the defects of the upper defect band located at E u T ¼ 2:75 ± 0:4 eV below the SiO 2 conduction band edge.…”

“…Furthermore, the oxide traps in every insulator are located within certain defect bands 23 with the maximum oxide trap density in the middle. 24 In particular, the number of oxide traps which are accessible for charge trapping depends on the energetic alignment of these defect bands relative to the conduction and valence band of the channel. Therefore, the determination of both density and energetic alignment of these defect bands is of utmost importance, especially for such unexplored system as BP/SiO 2 .…”

Optimization of inter-gate-dielectrics in hybrid float gate devices to reduce window instability during memory operations

“…Since there are a large number of electron traps in the high-k IGD layer [4][5][6][7]10], electron redistribution between FG and IGD and/or between IGD and CG could introduce window instability. Fig.…”

“…However, It is well known that the electron trap density in high-k materials is a few orders of magnitude higher than that in SiO 2 [4,5]. Efforts have been made to investigate the properties of these traps and the impact of their trapping/detrapping on memory operations [6][7][8][9][10]. Various window shifts during memory retention and endurance, read/pass disturbance operations in IGD-only or the conventional poly-Si FG cells have been observed and attributed to electron trapping/detrapping in the high-k stacks [11][12][13].…”

A Discharge-Based Pulse Technique for Probing the Energy Distribution of Positive Charges in Gate Dielectric

“…A modern pMOSFET typically operates with the Fermi-level at the interface below the top edge of the valence band, where the CP cannot probe. The Charge Injection and Sensing (CIS) technique proposed recently [11] requires no new trap generation and all the traps being charged and discharged repeatedly. However, these conditions cannot be met for PCs in pMOSFETs.…”