Transposable 3T-SRAM Synaptic Array Using Independent Double-Gate Feedback Field-Effect Transistors

Woo, Sola; Cho, Jinsun; Lim, Doohyeok; Cho, Kyoungah

doi:10.1109/ted.2019.2939393

Cited by 17 publications

(21 citation statements)

References 21 publications

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“…Among these neuron devices and circuits, our neuron device using a gated p–n–p–n diode structure is the most energy-efficient owing to its low energy consumption (4.5 × 10 −15 J), high firing frequency (~ 8 MHz), and absence of external bias voltage; note that neuron devices and circuits including our neuron device require peripheral circuits receiving synaptic pulses and delivering firing voltages. Our neuron device can implement a neuromorphic system by bidirectionally connecting with transposable synapstic SRAM using feedback field-effect transistor, and enables fast information transfer due to its high firing frequency 30 . Furthermore, our neuron device that is in normally-off state until synaptic pulses (analog and digital input signals) reach this device achieves zero standby power without external bias voltage.…”

Section: Resultsmentioning

confidence: 99%

Neural oscillation of single silicon nanowire neuron device with no external bias voltage

Woo

Kim

2022

Sci Rep

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In this study, we perform simulations to demonstrate neural oscillations in a single silicon nanowire neuron device comprising a gated p–n–p–n diode structure with no external bias lines. The neuron device emulates a biological neuron using interlinked positive and negative feedback loops, enabling neural oscillations with a high firing frequency of ~ 8 MHz and a low energy consumption of ~ 4.5 × 10−15 J. The neuron device provides a high integration density and low energy consumption for neuromorphic hardware. The periodic and aperiodic patterns of the neural oscillations depend on the amplitudes of the analog and digital input signals. Furthermore, the device characteristics, energy band diagram, and leaky integrate-and-fire operation of the neuron device are discussed.

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Section: Resultsmentioning

confidence: 99%

Neural oscillation of single silicon nanowire neuron device with no external bias voltage

Woo

Kim

2022

Sci Rep

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“…Doohyeok Lim, Kyoungah Cho, and Sangsig Kim* DOI: 10.1002/admt.202101504 quasi-nonvolatile memory devices, [22] and neuromorphic devices. [24][25][26][27] Specifically, switchable memory operations in silicon transistors demonstrate the possibility of a dual function of memory and logic. [28] Recently, applications in logic-in-memory have been investigated via computer simulations.…”

Section: Reconfigurable Logic-in-memory Using Silicon Transistorsmentioning

confidence: 99%

“…[ 18–20 ] Consequently, it is an attractive choice for next‐generation electronic devices, such as steep switching transistors, [ 15,21–23 ] quasi‐nonvolatile memory devices, [ 22 ] and neuromorphic devices. [ 24–27 ] Specifically, switchable memory operations in silicon transistors demonstrate the possibility of a dual function of memory and logic. [ 28 ] Recently, applications in logic‐in‐memory have been investigated via computer simulations.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Logic‐in‐Memory Using Silicon Transistors

Lim

Cho

Kim

2022

Adv Materials Technologies

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In this paper, a novel reconfigurable logic‐in‐memory built using silicon transistors is proposed. The silicon transistor can be reconfigured as p‐ or n‐switchable memory by controlling the polarity of the gate inputs. These electrical characteristics are enabled by utilizing holes or electrons as the majority charge carriers for the positive feedback loop. The reconfigurable logic‐in‐memory functions of the NOT and YES gates with the same cell comprising a silicon transistor and load resistor are demonstrated. Moreover, it is revealed that a two‐input reconfigurable logic‐in‐memory cell, based on two silicon transistors and a load resistor, functions as negative‐AND and OR gates. This novel reconfigurable logic‐in‐memory technology can facilitate the development of next‐generation low‐power and high‐performance computing.

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“…Therefore, it can be used as a logic and memory device with the same structure. Various applications of FBFET were studied, such as using it as a logic device, a memory device, and a neuron circuit [ 24 , 25 , 26 , 27 , 28 , 29 , 30 ]. In the previous study, we investigated electrical coupling between vertically stacked FBFETs in the monolithic 3-dimensional inverter (M3DINV) with FBFETs, in terms of device characteristics [ 31 ].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

2020

Micromachines

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The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

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Transposable 3T-SRAM Synaptic Array Using Independent Double-Gate Feedback Field-Effect Transistors

Cited by 17 publications

References 21 publications

Neural oscillation of single silicon nanowire neuron device with no external bias voltage

Neural oscillation of single silicon nanowire neuron device with no external bias voltage

Reconfigurable Logic‐in‐Memory Using Silicon Transistors

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

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