Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

Abstract

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

A Monolithic 3-Dimensional Static Random Access Memory Containing a Feedback Field Effect Transistor

“…Finally, this positive feedback between the electrons and the holes injection causes the energy band of all the regions align, as shown in Figure 2 c. Figure 3 shows the drain-source current of the NFBFET ( I DS-NFBFET ) versus V WL1 . There is an abrupt increment of the NFBFET current at V WL1 = 0.17 V. The hysteresis characteristic, which is the threshold voltage difference between forward and reverse, can be controlled by the doping profile of the channel region [ 33 ]. For the FBFET-SRAM operation, the very large memory window or non-turn-off characteristics by the gate-field, are required for maintaining the reading ‘ON’ current level, as shown in Figure 3 .…”

Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD

“…For the M3D structure, an FD-SOI FET structure is used for the NFBFET. This optimal structure of the NFBFET has been researched already [38], and the structure was used for this M3D-NVM-FBFET. The M3D-NVM-FBFET can be fabricated based on the elaboration step of previous work [39], and deposition of the ONO layer must be added before deposition of the gate material in the fabrication flow [40].…”

“…The electrical characteristics of the top-layer transistor were changed due to electrical coupling by the bottom-layer transistors or MIVs. The electrical coupling effects of the various circuits configured with MOSFETs [35], junction-less FETs [36,37], and FBFETs [38,39] have already been investigated. In the case of the NVM-FBFET, the investigation of the electrical coupling has not been conducted yet.…”

Logic and memory functions of an inverter comprising reconfigurable double gated feedback field effect transistors

“…To demonstrate the LIM operation, transient simulations are performed through mixed-mode technology computer-aided design (TCAD) simulation. Moreover, by applying a reset operation, the inverter exhibits the LIM operation without the output voltage loss, a common problem in the FBFET-based inverters 12 , 15 .…”