Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

“…MOS transistor mismatch can be defined as the variation in drain current for identically designed devices under similar bias conditions (Yuan, Shimizu, Mahalingam, Brown, and Habib 2011). The parameter variance is dependent on device area WL and separation distance D x .…”

Section: The Mismatch Of Mosfetmentioning

confidence: 99%

Model and physical implementation of multi-port PUF in 65 nm CMOS

Zhang

Wang

et al. 2013

International Journal of Electronics

View full text Add to dashboard Cite

In modern cryptographic systems, multi-port physically unclonable function (MPUF) is an efficient mechanism for many security applications, which extracts secret information inherently embedded in the unclonable physical variations and generates multiple secret keys. In this article, we propose an explicit analytic MPUF model, which is useful in predicting the effect of parameter changes on the state as well as in optimizing the design of PUF. Then, a novel MPUF based on register file is designed and fabricated in TSMC low-power 65 nm CMOS technology. There are four ports in the MPUF, and each port produces a 256-bit key. The chip has an area of 0.045 mm 2 , and has a peak clock frequency of 1.25 GHz at 1.2 V. The average power consumption is 13.8 mW at 27 C. Being multi-ports technology and high operation frequency, the throughput of MPUF improves about 50 times compared to the other works. We carry out a robust test by varying the operational conditions such as supply voltage, temperature and noise. The measured results show that the reliability achieves 98.1% at worse case and has a certain improvement compared with the proposed works. The reliability operates at an acceptable range in integrated circuit identification (ICID).

show abstract

“…These manufacturing process variations are effectively captured at the MOS transistor device level as variation in the threshold voltage (V th ) of the MOS transistors. Recent research [3] has shown that the threshold voltage variation can be modeled as a normal distribution, N µ V th , σ 2 V th with variance (σ 2 V th ), normalized with respect to its mean value is given by σ V th…”

Section: Modeling Process Variation a Threshold Voltage Variationmentioning

confidence: 99%

Impact of process variations on computers used for image processing

Sindia

Dai

Agrawal

et al. 2012

2012 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

Abstract-Manufacturing process variations (PV) of transistors in the deep-submicron regime present the single biggest design challenge for large die size VLSI circuits such as processor arrays, GPUs, and FPGAs. However, there are a few applications in signal processing, such as image processing, and speech processing, where errors in computation by the underlying hardware could be tolerated or corrected off-line with readily available image restoration algorithms. In this paper, we qualitatively and quantitatively evaluate the effect of process variation in the underlying hardware (for different technology nodes) on a high level application program such as image processing. We rely on gate level simulation, of the data-path of an image processor comprising of a dedicated multiply-accumulate (MAC) array of size 256 × 256, with individual gate delays of the processor sampled from a delay distribution as appropriate for each technology node. Our results show that processing images with PV degraded hardware in technologies beyond 65nm is discernible to the human eye; image quality degrades further at 45nm, and is of unacceptable quality at 32nm and beyond. We also use image restoration algorithms to restore the images corrupted due to processing on PV degraded hardware. Our results show that with standard restoration algorithms, even images processed with high levels of PV (as in 32nm) can be restored to almost the same quality as the image processed on fault-free hardware.

show abstract

Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

Cited by 47 publications

References 18 publications

Invited talk: Noise and mismatch in sub 28nm silicon processes

Invited talk: Noise and mismatch in sub 28nm silicon processes

Model and physical implementation of multi-port PUF in 65 nm CMOS

Impact of process variations on computers used for image processing

Contact Info

Product

Resources

About