Impact of process variations on computers used for image processing

Abstract

Abstract-Manufacturing process variations (PV) of transistors in the deep-submicron regime present the single biggest design challenge for large die size VLSI circuits such as processor arrays, GPUs, and FPGAs. However, there are a few applications in signal processing, such as image processing, and speech processing, where errors in computation by the underlying hardware could be tolerated or corrected off-line with readily available image restoration algorithms. In this paper, we qualitatively and quantitatively evaluate the effect of process variation in the underlying hardware (for different technology nodes) on a high level application program such as image processing. We rely on gate level simulation, of the data-path of an image processor comprising of a dedicated multiply-accumulate (MAC) array of size 256 × 256, with individual gate delays of the processor sampled from a delay distribution as appropriate for each technology node. Our results show that processing images with PV degraded hardware in technologies beyond 65nm is discernible to the human eye; image quality degrades further at 45nm, and is of unacceptable quality at 32nm and beyond. We also use image restoration algorithms to restore the images corrupted due to processing on PV degraded hardware. Our results show that with standard restoration algorithms, even images processed with high levels of PV (as in 32nm) can be restored to almost the same quality as the image processed on fault-free hardware.

Variation-aware approaches with power improvement in digital circuits

“…Besides, all the added circuits are themselves source of variation. The aforementioned works only consider variation with regard to delay; however, by 2026 power consumption for portable devices will be twice of the defined goal, and leakage power of integrated circuits will increase by eight times until 2016 [55]. This is why we have considered variation impacts of power, delay and PDP.…”

“…Thanks to this algorithm, we propose three approaches, namely variation-aware transistor sizing (VATS), variation-aware dual-V dd (VADVD), and variation-aware dual-V th (VADVT). To evaluate variation impacts, using this algorithm, we have adopted some mathematical formulae from [55]. Using Monte Carlo simulation and Gaussian distribution for each of the parameters, we extract power, delay and PDP values.…”

Towards spatial fault resilience in array processors

“…Another model used for emulating process variation induced or other defects in CMOS circuits using a probabilistic switching framework is due to Palem [7]. In a recent paper [9], we proposed the use of nonlinear median filters for off-line image restoration of images degraded by processing on a PV degraded hardware.…”