Transistor-Level Optimization of Supergates

Kagaris, Dimitris; Haniotakis, T.

doi:10.1109/isqed.2006.139

Cited by 4 publications

(15 citation statements)

References 8 publications

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“…To provide a comparison measure, we report here results obtained for the four functions F 4 , F 5 , F 6 and F 13 proposed in [3] and used also in [3,28,8]. Table 1 contains the [3], Columns 4 and 5 give the T count and corresponding S cost for the diagrams obtained in [8], and Columns 6 and 7 give the T count and corresponding S cost for the diagrams obtained by the proposed approach. The corresponding percentage gains (in power consumption cost) and overheads (in transistor count) of the proposed approach over [3] and [8] are reported in Table 2.…”

Section: Resultsmentioning

confidence: 99%

“…For further illustration, the diagrams for functions F4 and F6 obtained by the approach in [8], which targets transistor count reduction only, are shown in Fig. 2b and Fig.…”

Section: Resultsmentioning

confidence: 99%

“…The placement is done by considering three alternatives ("parallel," "splice," and "bridge") as was done in [8]. This part is described below as procedure PLACE(D, τ ).…”

Section: The Synthesis Techniquementioning

confidence: 99%

“…"Valid" means that if the candidate placement is selected to be included in the currently constructed diagram, the latter will not have any unwanted terms ("escape" or "sneak" paths). These alternatives are described in [8].…”

Section: The Synthesis Techniquementioning

confidence: 99%

“…That is, the power minimization is implicit in these methodologies. Two main approaches exist: factorization methods [5,1,2,3,18] and graph-oriented methods [6,27,10,28,13,23,8]. All these methodologies try to minimize the total number of transistors but they do not take into account that certain inputs are more critical (i.e., have higher switching activity) than others.…”

Section: Introductionmentioning

confidence: 99%

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Transistor-Level Synthesis for Low-Power Applications

Kagaris

Haniotakis

2007

8th International Symposium on Quality Electronic Design (ISQED'07)

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An important factor which greatly affects the power consumption and the delay of a circuit is the input capacitance of its gates. High input capacitances increase the power consumption as well as the time for charging and discharging the inputs. Current approaches address this problem either through gate-level only resynthesis and optimization, or indirectly through transistor-level synthesis aimed for transistor count reduction. In this paper a method is presented to synthesize complex gates at the transistor level with explicit consideration of the switching activity profile for the gate. The method finds a power efficient implementation by giving priority to transistor inputs with higher switching activity, while keeping the overall number of required transistors low. Experimental results demonstrate the benefit of the approach.

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Section: Resultsmentioning

confidence: 99%

“…For further illustration, the diagrams for functions F4 and F6 obtained by the approach in [8], which targets transistor count reduction only, are shown in Fig. 2b and Fig.…”

Section: Resultsmentioning

confidence: 99%

“…The placement is done by considering three alternatives ("parallel," "splice," and "bridge") as was done in [8]. This part is described below as procedure PLACE(D, τ ).…”

Section: The Synthesis Techniquementioning

confidence: 99%

Section: The Synthesis Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Transistor-Level Synthesis for Low-Power Applications

Kagaris

Haniotakis

2007

8th International Symposium on Quality Electronic Design (ISQED'07)

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Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering

Cardoso

Rosa

Marques³

et al. 2008

9th International Symposium on Quality Electronic Design (Isqed 2008)

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This paper presents a method for speeding-up ASICs by transistor reordering. The proposed method can be applied to a variety of logic styles and transistor topologies. The rationale of the obtained gains is explained through logical effort concepts. When applied to circuits based on 4-input networks, which is the case of many structured-ASIC or FPGA technologies, significant performance gains are obtained at a small area expense. This observation points out that our method can be of special interest when migrating FPGAs to ASICs. The logical effort effects on networks derived from BDDs illustrated in this paper can be exploited in a much broader range of designs.

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Switch level optimization of digital CMOS gate networks

Rosa

Schneider

Ribas

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

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This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of CMOS logic gate networks. Different properties of transistor networks are used to explain features and limitations of different methods. We describe which figures of merit, including the logical effort, affect the design quality of cell transistor networks. Further, we compare six different approaches that generate transistor networks, including two with guaranteed theoretical minimum length transistor chains. This comparison shows that minimum length chains reduce the logical effort of the networks.

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Transistor-Level Optimization of Supergates

Cited by 4 publications

References 8 publications

Transistor-Level Synthesis for Low-Power Applications

Transistor-Level Synthesis for Low-Power Applications

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering

Switch level optimization of digital CMOS gate networks

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