This paper presents the 15nm FinFET-based Open Cell Library (OCL) and describes the challenges in the methodology while designing a standard cell library for such advanced technology node. The 15nm OCL is based on a generic predictive state-of-the-art technology node. The proposed cell library is intended to provide access to advanced technology node for universities and other research institutions, in order to design digital integrated circuits and also to develop cell-based design flows, EDA tools and associated algorithms. Developing a 15nm standard cell library brings out design challenges which are not present in previous technology nodes. Some of these challenges include doublepatterning for both metal and poly layers, a very restrictive set of physical design rules, and the demand for lithographyfriendly patterns. This paper discusses the development of the library considering the challenges associated with advanced technology nodes.
Abstract-A new micromachined planar spiral inductor, with the strips suspended individually, has been fabricated in standard GaAs high electron-mobility transistor monolithic-microwave integrated-circuit technology through maskless front-side bulk micromachining. The electronic compatibility, the use of industrial integrated-circuit production lines, the straightforward and low-cost additional procedure for structure releasing, and the very short etching time required to do such are the principal features related to such a novel inductor structure. Moreover, the air-gap layer created underneath the device and between the strips significantly reduces shunt and fringing parasitic capacitances, consequently increasing the performance and operating frequency range. Experimental measurements, carried out up to 15 GHz, before and after micromachining, showed for a 12-nH inductor an increase of the maximum factor from 5 (at 3 GHz) to about 20 (at 7 GHz), while the self-resonant frequency was shifted from 5 to 13 GHz. Furthermore, a structure with two interleaved spiral inductors, in a 1 : 1 transformer-like configuration, was also fabricated, and its performance was verified as well in order to demonstrate the promising performance improvements provided by the proposed device. Finally, heating and mechanical characteristics associated with freestanding microstructures are briefly evaluated using finite-element method simulations.
Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.
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