Abstract-A new micromachined planar spiral inductor, with the strips suspended individually, has been fabricated in standard GaAs high electron-mobility transistor monolithic-microwave integrated-circuit technology through maskless front-side bulk micromachining. The electronic compatibility, the use of industrial integrated-circuit production lines, the straightforward and low-cost additional procedure for structure releasing, and the very short etching time required to do such are the principal features related to such a novel inductor structure. Moreover, the air-gap layer created underneath the device and between the strips significantly reduces shunt and fringing parasitic capacitances, consequently increasing the performance and operating frequency range. Experimental measurements, carried out up to 15 GHz, before and after micromachining, showed for a 12-nH inductor an increase of the maximum factor from 5 (at 3 GHz) to about 20 (at 7 GHz), while the self-resonant frequency was shifted from 5 to 13 GHz. Furthermore, a structure with two interleaved spiral inductors, in a 1 : 1 transformer-like configuration, was also fabricated, and its performance was verified as well in order to demonstrate the promising performance improvements provided by the proposed device. Finally, heating and mechanical characteristics associated with freestanding microstructures are briefly evaluated using finite-element method simulations.
A novel free-standing planar spiral inductor with reduced parasitic capacitances is proposed by suspending individually the strips, through a maskless front-side bulk micromachining compatible with a commercial GaAs HEMT monolithic microwave integrated circuit (MMIC) technology. Suspended structures have been fabricated and characterized at frequencies up to 15 GHz, showing quality factors of up to 16 and self-resonant frequency superior to 16 GHz for a 4.8 nH inductor. Moreover, since the standard IC process as well as the unconcerned electronic circuits are not influenced by micromachining, such devices are directly useful to enhance RF circuits, like matching networks, filters, and low-noise amplifiers
This paper presents a transistor-level verification flow to detect electrical overstress, static leakage and ESD-CDM issues in large low power SoC circuits. With innovative features like Spice patterns recognition and static voltage propagation by Calibre® PERC™, this approach brings significant added value to standard digital checkers that cannot capture some parts of the design in essence, such as analog IPs or third-party IPs designed outside power-intent driven flows. The results obtained on a 32nm CMOS circuit using multiple separate supplies with body biasing strategy, demonstrate the ability of this solution to cope with complex design architectures. As a matter of fact, some severe issues like hundreds of missing level shifters and weak input stages inside isolation cells were detected in few hours.
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