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Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.

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This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries.

This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of CMOS logic gate networks. Different properties of transistor networks are used to explain features and limitations of different methods. We describe which figures of merit, including the logical effort, affect the design quality of cell transistor networks. Further, we compare six different approaches that generate transistor networks, including two with guaranteed theoretical minimum length transistor chains. This comparison shows that minimum length chains reduce the logical effort of the networks.