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In this paper the implementation of a compact static memory library, called CeidMem, is presented. The library is based on the UMC technology and the 65nm low leakage process. The library is complete having basic memory cells, sense amplifiers, read/write circuitry and data bus precharge units. Moreover memory circuits are presented and their structure is explained. In conclusion, a complete example design which uses CeidMem as in chip level one cache, is analysed and simulated in order to confirm the correct functionality and behaviour of the library.

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In this paper, a new data reading technique for a bus of lines is proposed for fast operation. The proposed method utilizes multiple reference voltages available within a line's receiving logic and the initial conditions of wires in order to determine early and accurately the transmitted data of the current cycle. The presented technique does not require repeater insertion for reasonably long lines and it can significantly accelerate signal propagation. Experimental results are given in the 65 nm CMOS process for interconnects of various lengths.